Direct conversion receiver and dc offset reducing method

• US 20040097212A1
• Filed: 08/28/2003
• Published: 05/20/2004
• Est. Priority Date: 01/29/2002
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Obara, Toshio, Matsumoto, Hidenori
• Granted Patent: US 7,171,185 B2
• Time in Patent Office: Days
• US Class Current: 455/296
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04B 2201/70707 Efficiency-related aspects
• CPC Class Codes: H04L 25/06 Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
• CPC Class Codes: H04L 27/3809 Amplitude regulation arrangements

Abstract

A determining section (18) and gain variation amount detecting section (9) detect a period having a possibility of a DC-component offset in an internal circuit of a direct conversion receiver increasing beyond an allowable value due to AGC operation, and during the period, a cut-off frequency of each of high-pass filters (12a to 12d) is set at a frequency higher than that in general operation, thereby rapidly converging transient responses of signals passed through the high-pass filters, while controlling precisely operation timings of reception power measuring section (16), gain calculating section (22), gain control section (23) and circuit power supply control section (24) composing an AGC loop, whereby the DC offset is prevented from increasing and stable circuit operation is assured. It is thereby possible to achieve further reductions in size and power consumption of a CDMA receiver using the direct conversion receiver.

Claims

1. A DC offset reducing method of reducing a DC offset occurring in a direct conversion receiver, comprising:

detecting a period of time having a high possibility of increasing a DC offset; and

setting a time constant of a filter for cutting off a DC component existing on a signal path at a value smaller than that in general operation during the period of time, and thereby converging a transient response of a signal passed through the filter rapidly.

2. The DC offset reducing method according to claim 1, wherein the period of time having a high possibility of increasing a DC offset is detected, based on that a variation amount in gain exceeds a predetermined value, the gain for which is set a variable gain amplifier that is a structural element of an AGC loop, or that the direct conversion receiver is currently in either of a period immediately after the power is supplied, a period immediately after the receiver is activated in intermittent reception, and a period immediately after activating measurement of a different frequency.

3. An AGC circuit in a direct conversion receiver which multiplies a received high-frequency signal by a local signal with a frequency substantially the same as that of the high-frequency signal to directly convert into a baseband signal, amplifies the baseband signal using a baseband variable gain amplifying circuit having as structural elements a variable gain amplifier, low-pass filter and a high-pass filter with variable cut-off frequencies for cutting off a DC component, and performs A/D conversion and demodulation on the resultant, comprising:

a filter control section which switches a cut-off frequency of the high-pas filter to a frequency higher than that in general operation, and thereby decreases a time constant of the high-pass filter to converge a DC variation at high speed when a variation amount in gain exceeds a predetermined amount, the gain for which set is the variable gain amplifier that is a structural element of an AGC loop, or the direct conversion receiver is currently in either of a period immediately after the power is supplied, a period immediately after the receiver is activated in intermittent reception, and a period immediately after activating measurement of a different frequency.

10. A CDMA receiver provided with the AGC circuit in the direct conversion receiver according to claim 3.

4. An AGC circuit in a direct conversion receiver which multiplies a received high-frequency signal by a local signal with a frequency substantially the same as that of the high-frequency signal to directly convert into a baseband signal, amplifies the baseband signal using a baseband variable gain amplifying circuit having as structural elements a variable gain amplifier, low-pass filter and a high-pass filter with variable cut-off frequencies for cutting off a DC component, and performs A/D conversion and demodulation on the resultant, comprising:

a power measuring section that measures reception power based on a signal subjected to A/D conversion;

a gain calculating section that calculates a gain of the variable gain amplifier using information of a difference between measured reception power and a target convergence value;

a gain control section that controls the gain of the variable gain amplifier based on the calculated gain;

a filter control section that has a function of switching a cut-off frequency of the high-pass filter between at least high-and-low two frequencies; and

a gain variation amount detecting section which, when detecting that the gain of the variable gain amplifier varies by an mount exceeding a predetermined amount as a result of control by the gain control section, notifies the filter control section of the detection,

wherein upon receiving a notification of the detection from the gain variation amount detecting section, the filter control section switches the cut-off frequency of the high-pass filter to a high frequency.

5. The AGC circuit in the direct conversion receiver according to claim 4, wherein during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency, the gain calculating section and the gain control section perform at least one of processing for increasing a variation width in gain per-one update and for decreasing a period of the update.

6. The AGC circuit in the direct conversion receiver according to claim 4, wherein the filter control section switches the cut-off frequency of the high-pass filter to the high frequency and then switches the cut-off frequency to a low frequency again, and the power measuring section does not measure reception power during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency in a predetermined period in measuring average reception power for the predetermined period.

11. A CDMA receiver provided with the AGC circuit in the direct conversion receiver according to claim 4.

7. An AGC circuit in a direct conversion receiver which multiplies a received high-frequency signal by a local signal with a frequency substantially the same as that of the high-frequency signal to directly convert into a baseband signal, amplifies the baseband signal using a baseband variable gain amplifying circuit having as structural elements a variable gain amplifier, low-pass filter and a high-pass filter with variable cut-off frequencies for cutting off a DC component, and performs A/D conversion and demodulation on the resultant, comprising:

a power measuring section that measures reception power based on a signal subjected to A/D conversion;

a gain calculating section that calculates a gain of the variable gain amplifier using information of a difference between measured reception power and a target convergence value;

a gain control section that controls the gain of the variable gain amplifier based on the calculated gain;

a filter control section that has a function of switching a cut-off frequency of the high-pass filter between at least high-and-low two frequencies; and

a determining section which determines whether or not a state has a high possibility of increasing a DC offset of a signal passed through the high-pass filter, based on information contained in a demodulated signal, or based on an operation state of the direct conversion receiver, and which notifies the determination result to the filter control section,

wherein upon receiving the notification from the determining section, the filter control section switches the cut-off frequency of the high-pass filter to the high frequency.

8. The AGC circuit in the direct conversion receiver according to claim 7, wherein during the period of time the cut-off frequency of the high-pass filter is switched to the high frequency, the gain calculating section and the gain control section perform at least one of processing for increasing a variation width in gain per-one update and for decreasing a period of the update, and implement AGC faster than that in general operation.

9. The AGC circuit in the direct conversion receiver according to claim 7, wherein the filter control section switches the cut-off frequency of the high-pass filter to the high frequency and then switches the cut-off frequency to a low frequency again, and the power measuring section does not measure reception power during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency in a predetermined period in measuring average reception power for the predetermined period.

12. A CDMA receiver provided with the AGC circuit in the direct conversion receiver according to claim 7.

13. A baseband variable gain amplifying circuit that is provided in a direction conversion receiver and that amplifies a baseband signal, comprising:

a variable gain amplifier that amplifies the baseband signal;

a high-pass filter that cuts off a DC component existing on a signal path of the baseband signal and that enables a cut-off frequency to be varied between at least low-and-high two frequencies;

a gain variation amount detecting section which detects that a variation amount in gain for which set is the variable gain amplifier exceeds a predetermined threshold; and

a filter control section that switches the cut-off frequency of the high-pass filter to a high frequency when the gain variation amount detecting section detects that the variation amount in gain exceeds the predetermined threshold.

14. A baseband variable gain amplifying circuit that is provided in a direction conversion receiver and that amplifies a baseband signal, comprising:

a variable gain amplifier that amplifies the baseband signal;

a high-pass filter that cuts off a DC component existing on a signal path of the baseband signal and that enables a cut-off frequency to be varied between at least low-and-high two frequencies; and

a filter control section that switches the cut-off frequency of the high-pass filter based on an AGC mode signal and a timing control signal of the direct conversion receiver.

15. A baseband variable gain amplifying circuit that is provided in a direction conversion receiver and that amplifies a baseband signal, comprising:

a variable gain amplifier that amplifies the baseband signal;

a high-pass filter that cuts off a DC component existing on a signal path of the baseband signal and that enables a cut-off frequency to be varied between at least low-and-high two frequencies;

a D/A converter that converts data of a gain for which the variable gain amplifier is set and digital data including data for instructing switching of the cut-off frequency of the high-pass filter into an analog signal; and

a filter control section that switches the cut-off frequency of the high-pass filter based on a signal corresponding to the data for instructing switching of the cut-off frequency.

16. A baseband variable gain amplifying circuit that is provided in a direction conversion receiver and that amplifies a baseband signal, comprising:

a variable gain amplifier that amplifies the baseband signal;

a high-pass filter that cuts off a DC component existing on a signal path of the baseband signal and that enables a cut-off frequency to be varied between at least low-and-high two frequencies;

a PLL synthesizer circuit;

an interface circuit that receives a digital control signal including designation data for designating an oscillation frequency of the PLL synthesizer circuit, while outputting an oscillation output output from the PLL synthesizer circuit as designated by the designation data, as a control signal for switching the cut-off frequency of the high-pass filter; and

a filter control section that switches the cut-off frequency of the high-pass filter, based on the control signal output from the interface circuit.

17. A baseband variable gain amplifying circuit that is provided in a direction conversion receiver and that amplifies a baseband signal, comprising:

a variable gain amplifier that amplifies the baseband signal;

a high-pass filter that cuts off a DC component existing on a signal path of the baseband signal and that enables a cut-off frequency to be varied between at least low-and-high two frequencies;

a circuit that turns ON/OFF a power supply of the baseband variable gain amplifying circuit; and

a filter control section that switches the cut-off frequency of the high-pass filter, using a change in the power supply of from OFF to ON by the circuit that turns ON/OFF of the power supply, as a trigger.