Cache system and cache memory control device controlling cache memory having two access modes

• US 20040098540A1
• Filed: 07/02/2003
• Published: 05/20/2004
• Est. Priority Date: 11/19/2002
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Itoh, Teruyuki, Okumura, Naoto
• Application Number:
  US10/610,763
• Publication Number:
  US 20040098540A1
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0877 Cache access modes
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A branch/prefetch judgement portion, in receipt of a branch request signal, sets a cache access mode switch signal to an “H” level. Thus, a cache memory operates in the 1-cycle access mode consuming a large amount of power. In receipt of a prefetch request signal, the branch/prefetch judgement portion sets the cache access mode switch signal to an “L” level. Thus, the cache memory operates in the 2-cycle access mode consuming less power.

Claims

1. A cache system, comprising:

a cache memory performing an operation to output stored data as accessed, during a first time period in a first access mode, and during a second time period that is longer than the first time period in a second access mode;

a processor performing pipeline processing of the data within said cache memory; and

an access mode control portion outputting to said cache memory one of a first access mode signal designating to operate in said first access mode and a second access mode signal designating to operate in said second access mode, based on presence/absence of pipeline stall in respective one of said access modes.

2. The cache system according to claim 1, wherein

said processor, after execution of a branch instruction, outputs a branch request signal and flushes the pipeline processing for a succeeding instruction, and

said access mode control portion, in receipt of said branch request signal, outputs said first access mode signal.

3. The cache system according to claim 2, comprising:

a plurality of queues holding instructions output from said cache memory; and

a queue control portion outputting a prefetch request signal when a last instruction in respective one of said queues is output;

said cache memory outputting at least three instructions simultaneously to any one of said queues, and

said access mode control portion, in receipt of said prefetch request signal, outputs said second access mode signal.

4. The cache system according to claim 2, comprising:

a plurality of queues holding instructions output from said cache memory; and

a queue control portion outputting a prefetch request signal when a last instruction in respective one of said queues is output;

said cache memory outputting a plurality of instructions simultaneously to any one of said queues,

said processor reading and executing the instructions from said queues, executing the branch instruction, and further outputting a branch destination address,

said access mode control portion, in receipt of the branch destination address, setting a flag in the case where the instruction of the branch destination address when stored in a queue becomes the last instruction in the relevant queue, and

in the case where said flag is set, said access mode control portion, in receipt of a prefetch request signal, outputting said first access mode signal and then canceling said flag.

5. The cache system according to claim 1, wherein

said processor, when decoding an instruction for storing data within a memory in a register, outputs a storage register number included in the relevant instruction,

said processor, when decoding an instruction succeeding said instruction and for referring to data in a register, outputs a reference register number included in the relevant instruction, and

said access mode control portion, in receipt of said storage register number and said reference register number, determines whether said storage register number and said reference register number match or not, and outputs said first access mode signal in the case of a match, and outputs said second access mode signal in the case of a mismatch.

6. The cache system according to claim 1, wherein said cache memory, in said first access mode, causes a plurality of ways to operate simultaneously to output a plurality of data items, and selects and outputs one of said plurality of data items during said first time period, and, in said second access mode, selects and causes one of the plurality of ways to operate to output data during said second time period.

7. A cache memory control device controlling a cache memory performing an operation to output stored data as accessed during a first time period in a first access mode and during a second time period that is longer than the first time period in a second access mode, comprising:

a judgement portion determining whether a processor, processing data within said cache memory by selecting and operating at one of a plurality of clock frequencies, is operating at a clock frequency of not lower than a prescribed value or operating at a clock frequency of less than said prescribed value; and

an access mode control portion outputting a first access mode signal designating said first access mode when said judgement portion determines that said processor is operating at the clock frequency of not lower than said prescribed value, and outputting a second access mode signal designating said second access mode when said judgement portion determines that said processor is operating at the clock frequency of less than said prescribed value.

8. The cache memory control device according to claim 7, wherein said cache memory, in said first access mode, causes a plurality of ways to operate simultaneously to output a plurality of data items and selects and outputs one of said plurality of data items during said first time period, and, in said second access mode, selects and causes one of the plurality of ways to operate to output data during said second time period.