Programmable processor and method with wide operations

• US 20040098548A1
• Filed: 12/19/2003
• Published: 05/20/2004
• Est. Priority Date: 08/16/1995
• Status: Active Grant

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig, Massalin, Alexia
• Granted Patent: US 7,301,541 B2
• Time in Patent Office: Days
• US Class Current: 711/165
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 : comprising data of variable length
• CPC Class Codes: G06F 9/30145 : Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30149 : of variable length instructions
• CPC Class Codes: G06F 9/3016 : Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 : of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/35 : Indirect addressing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4484 : Executing subprograms
• CPC Class Codes: G06F 9/45533 : Hypervisors; Virtual machine monitors
• CPC Class Codes: H03M 13/158 : Finite field arithmetic processing
• CPC Class Codes: H03M 13/4169 : using traceback H03M13/4192 takes precedence
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Claims

1. A method of performing a computation in a programmable processor, the programmable processor having a first memory system having a first data path width, and a second memory system and a third memory system each of the second memory system and the third memory system having a data path width which is greater than the first data path width, the method comprising the steps of:

copying a first memory operand portion from the first memory system to the second memory system, the first memory operand portion having the first data path width;

copying a second memory operand portion from the first memory system to the second memory system, the second memory operand portion having the first data path width and being catenated in the second memory system with the first memory operand portion, thereby forming first catenated data;

copying a third memory operand portion from the first memory system to the third memory system, the third memory operand portion having the first data path width;

copying a fourth memory operand portion from the first memory system to the third memory system, the fourth memory operand portion having the first data path width and being catenated in the third memory system with the third memory operand portion, thereby forming second catenated data; and

performing a computation of a single instruction using the first catenated data and the second catenated data.

2. The method of claim 1 wherein the step of performing a computation further comprises reading a portion of the first catenated data and a portion of the second catenated data each of which is greater in width than the first data path width and using the portion of the first catenated data and the portion of the second catenated data to perform the computation.

3. The method of claim 2 further comprising the step of specifying a memory address of each of the first catenated data and of the second catenated data within the first memory system.

4. The method of claim 3 further comprising the step of specifying a memory operand size and a memory operand shape of each of the first catenated data and the second catenated data.

5. The method of claim 2 further comprising the step of checking the validity of each of the first catenated data in the second memory system and the second catenated data in the third memory system, and, if valid, permitting a subsequent instruction to use the first and second catenated data without copying from the first memory system.

6. The method of claim 2 wherein the step of performing a computation further comprises performing a convolution of partitioned elements contained in the first catenated data with partitioned elements contained in the second catenated data, forming a convolution data, extracting a specified subfield of the convolution data and catenating extracted data, and forming a catenated result having a size equal to that of the functional unit data path width.

7. The method of claim 2, wherein the step of performing a computation further comprises performing a transform of partitioned elements contained in the first catenated data using coefficients contained in the second catenated data, thereby forming a transform data, extracting a specified subfield of the transform data, thereby forming an extracted data and catenating the extracted data.

8. A method of performing a computation in a programmable processor, the programmable processor having a first memory system having a first data path width, and a second and a third memory system having a data path width which is greater than the first data path width, the method comprising the steps of:

copying a first memory operand portion from the first memory system to the second memory system, the first memory operand portion having the first data path width;

copying a second memory operand portion from the first memory system to the second memory system, the second memory operand portion having the first data path width and being catenated in the second memory system with the first memory operand portion, thereby forming first catenated data;

performing a computation of a single instruction using the first catenated data and producing a second catenated data,

copying a third memory operand portion from the third memory system to the first memory system, the third memory operand portion having the first data path width and containing a portion of the second catenated data; and

copying a fourth memory operand portion from the third memory system to the first memory system, the fourth memory operand portion having the first data path width and containing a portion of the second catenated data, wherein the fourth memory operand portion is catenated in the third memory system with the third memory operand portion.

9. The method of claim 8 wherein the step of performing a computation further comprises the step of reading a portion of the first catenated data which is greater in width than the first data path width and using the portion of the first catenated data to perform the computation.

10. The method of claim 9 further comprising the step of specifying a memory address of each of the first catenated data and of the second catenated data within the first memory system.

11. The method of claim 10 further comprising the step of specifying a memory operand size and a memory operand shape of each of the first catenated data and the second catenated data.

12. The method of claim 9 further comprising the step of checking the validity of the first catenated data in the second memory system, and, if valid, permitting a subsequent instruction to use the first catenated data without copying from the first memory system.

13. The method of claim 8 wherein the step of performing a computation further comprises the step of performing a transform of partitioned elements contained in the first catenated data, thereby forming a transform data, extracting a specified subfield of the transform data, thereby forming an extracted data and catenating the extracted data, forming the second catenated data.

14. The method of claim 8 wherein the step of performing a computation further comprises the step of combining using Boolean arithmetic a portion of the extracted data with an accumulated Boolean data, combining partitioned elements of the accumulated Boolean data using Boolean arithmetic, forming combined Boolean data, determining the most significant bit of the extracted data from the combined Boolean data, and returning a result comprising the position of the most significant bit to a register.

15. The method of claim 8 further comprising manipulating a first and a second validity information corresponding to first and second catenated data, wherein after completion of an instruction specifying a memory address of first catenated data, the contents of second catenated data are provided to the first memory system in place of first catenated data.

16. A programmable processor comprising:

a first memory system having a first data path width;

a second memory system and a third memory system, wherein each of the second memory system and the third memory system have a data path width which is greater than the first data path width;

a first copying module configured to copy a first memory operand portion from the first memory system to the second memory system, the first memory operand portion having the first data path width, and configured to copy a second memory operand portion from the first memory system to the second memory system, the second memory operand portion having the first data path width and being catenated in the second memory system with the first memory operand portion, thereby forming first catenated data;

a second copying module configured to copy a third memory operand portion from the first memory system to the third memory system, the third memory operand portion having the first data path width, and configured to copy a fourth memory operand portion from the first memory system to the third memory system, the fourth memory operand portion having the first data path width and being catenated in the third memory system with the third memory operand portion, thereby forming second catenated data; and

a functional unit configured to perform computations using the first catenated data and the second catenated data.

17. The programmable processor of claim 16 wherein the functional unit is further configured to read a portion of each of the first catenated data and the second catenated data which is greater in width than the first data path width and use the portion of each of the first catenated data and the second catenated data to perform the computation.

18. The programmable processor of claim 17 wherein the functional unit is further configured to specify a memory address of each of the first catenated data and of the second catenated data within the first memory system.

19. The programmable processor of claim 18 wherein the functional unit is further configured to specify a memory operand size and a memory operand shape of each of the first catenated data and the second catenated data.

20. The programmable processor of claim 17 further comprising a control unit configured to check the validity of each of the first catenated data in the second memory system and the second catenated data in the third memory system, and, if valid, permitting a subsequent instruction to use each of the first catenated data and the second catenated data without copying from the first memory system.

21. The programmable processor of claim 16, wherein the functional unit is further configured to convolve partitioned elements contained in the first catenated data with partitioned elements contained in the second catenated data, forming a convolution data, extract a specified subfield of the convolution data and catenate extracted data, forming a catenated result having a size equal to that of the functional unit data path width.

22. The programmable processor of claim 16 wherein the functional unit is further configured to perform a transform of partitioned elements contained in the first catenated data using coefficients contained in the second catenated data, thereby forming a transform data, extract a specified subfield of the transform data, thereby forming an extracted data and catenate the extracted data.

23. A programmable processor comprising:

a first memory system having a first data path width,

a second memory system and a third memory system each of the second memory system and the third memory system having a data path width which is greater than the first data path width;

a first copying module configured to copy a first memory operand portion from the first memory system to the second memory system, the first memory operand portion having the first data path width, and configured to copy a second memory operand portion from the first memory system to the second memory system, the second memory operand portion having the first data path width and being catenated in the second memory system with the first memory operand portion, thereby forming first catenated data;

a second copying module configured to copy a third memory operand portion from the third memory system to the first memory system, the third memory operand portion having the first data path width and containing a portion of a second catenated data, and copy a fourth memory operand portion from the third memory system to the first memory system, the fourth memory operand portion having the first data path width and containing a portion of the second catenated data, wherein the fourth memory operand portion is catenated in the third memory system with the third memory operand portion; and

a functional unit configured to perform computations using the first catenated data and the second catenated data.

24. The programmable processor of claim 23 wherein the functional unit is further configured to read a portion of the first catenated data which is greater in width than the first data path width and use the portion of the first catenated data to perform the computation.

25. The programmable processor of claim 24 wherein the functional unit is further configured to specify a memory address of each of the first catenated data and of the second catenated data within the first memory system.

26. The programmable processor of claim 25 wherein the functional unit is further configured to specify a memory operand size and a memory operand shape of each of the first catenated data and the second catenated data.

27. The programmable processor of claim 24 further comprising a control unit configured to check the validity of the first catenated data in the second memory system, and, if valid, permitting a subsequent instruction to use the first catenated data without copying from the first memory system.

28. The programmable processor of claim 23 wherein the functional unit is further configured to transform partitioned elements contained in the first catenated data, thereby forming a transform data, extract a specified subfield of the transform data, thereby forming an extracted data and catenate the extracted data, forming the second catenated data.

29. The programmable processor of claim 23 wherein the functional unit is further configured to combine using Boolean arithmetic a portion of the extracted data with an accumulated Boolean data, combine partitioned elements of the accumulated Boolean data using Boolean arithmetic, forming combined Boolean data, determine the most significant bit of the extracted data from the combined Boolean data, and provide a result comprising the position of the most significant bit.

30. The programmable processor of claim 23 further comprising a control unit configured to manipulate a first and a second validity information corresponding to first and second catenated data, wherein after completion of an instruction specifying a memory address of first catenated data, the contents of second catenated data are provided to the first memory system in place of first catenated data.