System and software for catenated group shift instruction

• US 20040098567A1
• Filed: 11/14/2003
• Published: 05/20/2004
• Est. Priority Date: 08/16/1995
• Status: Active Grant

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Granted Patent: US 7,353,367 B2
• Time in Patent Office: Days
• US Class Current: 712/223
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/323 : for indirect branch instructions
• CPC Class Codes: G06F 9/3816 : Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the execution unit is operable to shift a subfield of each of the plurality of data elements by the shift amount to produce a second plurality of data elements; and provide the second plurality of data elements as a catenated result.

Claims

1. A data processing system comprising:

(a) a bus coupling components in the data processing system;

(b) an external memory coupled to the bus;

(c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising;

a virtual memory addressing unit;

an instruction path and a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and

an execution unit coupled to the instruction and data paths and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying both a shift amount and a register having a register width, the number of data elements in the first plurality of data elements being inversely related to the elemental width, the register containing a first plurality of data elements having an elemental width smaller than the register width, the shift amount configurable to an amount inclusively between zero and one less than the elemental width, the execution unit is operable to;

(i) shift a subfield of each of the first plurality of data elements by the shift amount to produce a second plurality of data elements; and

(ii) provide the second plurality of data elements as a catenated result.

2. The system of claim 1 wherein the catenated result is provided to a register.

3. The system of claim 1 wherein the shift amount is contained in a register specified by the instruction.

4. The system of claim 1 wherein the shift amount is contained in an immediate field of the instruction.

5. The system of claim 1 wherein each data element in the first plurality of data elements has a sign bit in a most significant bit position and wherein the execution unit is further operable to fill a shift amount number of most significant bits in each of the second plurality of data elements with the sign bit from a respective data element in the first plurality of data elements.

6. The system of claim 1 wherein the execution unit is further operable to fill a shift amount number of most significant bits in each of the second plurality of data elements with zeros.

7. The system of claim 1 wherein the execution unit is further operable to fill a shift amount number of most significant bits in each of the second plurality of data elements with a subfield from a respective location of the contents of an additional register.

8. The system of claim 1 wherein the catenated result has a width of 128 bits.

9. The system of claim 1 wherein the elemental width of each of the first plurality of data elements is 32 bits.

10. The system of claim 1 wherein the elemental width of each of the first plurality of data elements is 16 bits.

11. The system of claim 1 wherein an elemental width of each of the second plurality of data elements is equal to the elemental width of each of the first plurality of data elements.

12. The system of claim 1 wherein an elemental width of each of the second plurality of data elements is equal to twice the elemental width of each of the first plurality of data elements.

13. The system of claim 1 wherein an elemental width of each of the second plurality of data elements is equal to half the elemental width of each of the first plurality of data elements.

14. A computer-readable medium:

having instructions that cause a computer system to perform operations,

wherein at least some of the instructions comprise a group shift instruction for shifting data in a programmable processor, the group shift instruction;

specifying both a shift amount and a register having a register width, the register containing a first plurality of data elements having an elemental width smaller than the register width, the number of data elements in the first plurality of data elements being inversely related to the elemental width, the shift amount configurable to an amount inclusively between zero and one less than the elemental width;

shifting a subfield of each of the first plurality of data elements by the shift amount to produce a second plurality of data elements; and

providing the second plurality of data elements as a catenated result.

15. The computer-readable medium of claim 14 wherein the catenated result is provided to a register.

16. The computer-readable medium of claim 14 wherein the shift amount is contained in a register specified by the instruction.

17. The computer-readable medium of claim 14 wherein the shift amount is contained in an immediate field of the instruction.

18. The computer-readable medium of claim 14 wherein each data element in the first plurality of data elements has a sign bit in a most significant bit position and wherein the group shift instruction further comprises:

filling a shift amount number of most significant bits in each of the second plurality of data elements with the sign bit from a respective data element in the first plurality of data elements.

19. The computer-readable medium of claim 14 wherein the group shift instruction further comprises:

filling a shift amount number of bits in each of the second plurality of data elements with zeros.

20. The computer-readable medium of claim 14 wherein the group shift instruction further comprises:

filling a shift amount number of bits in each of the second plurality of data elements with a subfield from a respective location of the contents of an additional register.

21. The computer-readable medium of claim 14 wherein the catenated result has a width of 128 bits.

22. The computer-readable medium of claim 14 wherein the elemental width of each of the first plurality of data elements is 32 bits.

23. The computer-readable medium of claim 14 wherein the elemental width of each of the first plurality of data elements is 16 bits.

24. The computer-readable medium of claim 14 wherein an elemental width of each of the second plurality of data elements is equal to the elemental width of each of the first plurality of data elements.

25. The computer-readable medium of claim 14 wherein an elemental width of each of the second plurality of data elements is equal to twice the elemental width of each of the first plurality of data elements.

26. The computer-readable medium of claim 14 wherein an elemental width of each of the second plurality of data elements is equal to half the elemental width of each of the first plurality of data elements.

27. A computer data signal, embodied in a transmission medium:

having instructions that cause a computer system to perform operations,

wherein at least some of the instructions comprise a group shift instruction for shifting data in a programmable processor, the group shift instruction;

specifying both a shift amount and a register having a register width, the register containing a first plurality of data elements having an elemental width smaller than the register width, the number of data elements in the first plurality of data elements being inversely related to the elemental width, the shift amount configurable to an amount inclusively between zero and one less than the elemental width;

shifting a subfield of each of the first plurality of data elements by the shift amount to produce a second plurality of data elements; and

providing the second plurality of data elements as a catenated result.

28. The computer data signal of claim 27 wherein the catenated result is provided to a register.

29. The computer data signal of claim 27 wherein the shift amount is contained in a register specified by the instruction.

30. The computer data signal of claim 27 wherein the shift amount is contained in an immediate field of the instruction.

31. The computer data signal of claim 27 wherein each data element in the first plurality of data elements has a sign bit in a most significant bit position and wherein the group shift instruction further comprises:

filling a shift amount number of most significant bits in each of the second plurality of data elements with the sign bit from a respective data element in the first plurality of data elements.

32. The computer data signal of claim 27 wherein the group shift instruction further comprises:

filling a shift amount number of bits in each of the second plurality of data elements with zeros.

33. The computer data signal of claim 27 wherein the group shift instruction further comprises:

filling a shift amount number of bits in each of the second plurality of data elements with a subfield from a respective location of the contents of an additional register.

34. The computer data signal of claim 27 wherein the catenated result has a width of 128 bits.

35. The computer data signal of claim 27 wherein the elemental width of each of the first plurality of data elements is 32 bits.

36. The computer data signal of claim 27 wherein the elemental width of each of the first plurality of data elements is 16 bits.

37. The computer data signal of claim 27 wherein an elemental width of each of the second plurality of data elements is equal to the elemental width of each of the first plurality of data elements.

38. The computer data signal of claim 27 wherein an elemental width of each of the second plurality of data elements is equal to twice the elemental width of each of the first plurality of data elements.

39. The computer data signal of claim 27 wherein an elemental width of each of the second plurality of data elements is equal to half the elemental width of each of the first plurality of data elements.