Monent computation algorithms in VLSI system
First Claim
1. A method for reducing a parasitic graph for an interconnect model circuit, the parasitic graph comprising a plurality of nodes, comprising the steps of:
- (a) performing a depth-first-search on the graph;
(b) determining a degree of a deepest node with a smallest degree, wherein the node can have a degree of more than one;
(c) reducing the graph by eliminating the node; and
(d) recursively performing the determining step (b) and the reducing step (c) until the depth-first-search completes.
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Abstract
An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.
2 Citations
27 Claims
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1. A method for reducing a parasitic graph for an interconnect model circuit, the parasitic graph comprising a plurality of nodes, comprising the steps of:
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(a) performing a depth-first-search on the graph;
(b) determining a degree of a deepest node with a smallest degree, wherein the node can have a degree of more than one;
(c) reducing the graph by eliminating the node; and
(d) recursively performing the determining step (b) and the reducing step (c) until the depth-first-search completes. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for reducing a parasitic graph for an interconnect model circuit, the parasitic graph comprising a plurality of nodes, comprising the steps of:
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(a) performing a depth-first-search on the graph;
(b) determining a degree of a deepest node with a smallest degree, wherein the node can have a degree of more than one;
(c) reducing the graph by eliminating the node, wherein the reducing comprises;
(c1) determining a matrix, wherein each entry of the matrix represents an edge of the graph, (c2) changing the matrix such that a voltage at the node is no longer coupled to other nodes in the graph, and (c3) reducing the graph by eliminating the node, wherein the changed matrix represents edges of the reduced graph; and
(d) recursively performing the determining step (b) and the reducing step (c) until the depth-first-search completes. - View Dependent Claims (8, 9, 10, 11)
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12. A method for reducing a parasitic graph for a interconnect model circuit, he parasitic graph comprising a plurality of nodes, comprising the steps of:
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(a) performing a first depth-first-search on the graph;
(b) determining a degree of a deepest node with the smallest degree, wherein the node can have a degree of one or two;
(c) reducing the graph by eliminating the node;
(d) recursively performing the determining step (b) and the reducing step (c) until the first depth-first-search completes;
(e) determining if nodes of degrees of three or more remain in the reduced graph;
(f) performing a second depth-first-search on the reduced graph, if nodes of degrees of three of more remain in the reduced graph;
(g) determining a degree for another deepest node with a smallest degree, wherein the other node can have a degree of three or more;
(h) further reducing the reduced graph by eliminating the other node; and
(i) recursively performing the determining step (g) and the further reducing step (h) until the second depth-first-search completes.
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13. A computer readable medium with program instructions for reducing a parasitic graph for an interconnect model circuit, the parasitic graph comprising a plurality of nodes, comprising the instructions for:
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(a) performing a depth-first-search on the graph;
(b) determining a degree of a deepest node with a smallest degree, wherein the node can have a degree of more than one;
(c) reducing the graph by eliminating the node; and
(d) recursively performing the determining instruction (b) and the reducing instruction (c) until the depth-first-search completes.
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14. A method for calculating moments for an interconnect circuit model, comprising the steps of:
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(a) creating at least one parasitic graph for the interconnect circuit model, wherein the at least one parasitic graph comprises a plurality of nodes;
(b) determining if the at least one parasitic graph has been reduced;
(c) reducing the at least one parasitic graph if the at least one parasitic graph has not been reduced, wherein the reducing comprises;
(c1) performing a depth-first-search on the at least one parasitic graph, (c2) determining a degree of a deepest node with a smallest degree, wherein the node can have a degree of more than one, (c3) reducing the at least one parasitic graph by eliminating the node, and (c4) recursively performing the determining step (c2) and the reducing step (c3) until the depth-first-search completes; and
(d) computing moments for the interconnect circuit model utilizing the reduced graph. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 24, 25, 26)
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27. A computer readable medium with program instructions for calculating moments for an interconnect circuit model, comprising the instructions for:
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(a) creating at least one parasitic graph for the interconnect circuit model, wherein the at least one parasitic graph comprises a plurality of nodes;
(b) determining if the at least one parasitic graph has been reduced;
(c) reducing the at least one parasitic graph if the at least one parasitic graph has not been reduced, wherein the reducing comprises;
(c1) performing a depth-first-search on the at least one parasitic graph, (c2) determining a degree of a deepest node with a smallest degree, wherein the node can have a degree of more than one, (c3) reducing the at least one parasitic graph by eliminating the node, and (c4) recursively performing the determining step (c2) and the reducing step (c3) until the depth-first-search completes; and
(d) computing moments for the interconnect circuit model utilizing the reduced graph.
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Specification