Thin film transistor array panel and manufacturing method thereof
First Claim
1. A thin film transistor array panel comprising:
- first and second gate members connected to each other;
a gate insulating layer formed on the first and the second gate members;
first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively;
first and second source members connected to each other and located near the first and the second semiconductor members, respectively;
first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and
a pixel electrode connected to the first and the second drain members, wherein the first gate member, the first semiconductor member, the first source member, and the first drain members form a first thin film transistor, and the second gate member, the second semiconductor member, the second source member, and the second drain members form a second thin film transistor.
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Accused Products
Abstract
A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.
20 Citations
11 Claims
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1. A thin film transistor array panel comprising:
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first and second gate members connected to each other;
a gate insulating layer formed on the first and the second gate members;
first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively;
first and second source members connected to each other and located near the first and the second semiconductor members, respectively;
first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and
a pixel electrode connected to the first and the second drain members, wherein the first gate member, the first semiconductor member, the first source member, and the first drain members form a first thin film transistor, and the second gate member, the second semiconductor member, the second source member, and the second drain members form a second thin film transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of manufacturing a thin film transistor array panel, the method comprising:
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forming a pair of first and second gate members;
forming a gate insulating layer on the first and the second gate members;
forming a pair of first and second semiconductor members on the gate insulating layer;
forming a pair of first and second source members and a pair of first and second drain members; and
forming a pixel electrode connected to the first and the second drain members, wherein at least one pair of the first and the second gate members, the first and the second semiconductor members, the first and the second source members, and the first and the second drain members are formed using a divisional light exposure, and a boundary line between shots in the divisional light exposure is located between the first gate member and the second gate member, between the first semiconductor member and the second semiconductor member, between the first source member and the second source member, or between the first drain member and the second drain member. - View Dependent Claims (11)
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Specification