USE OF AMORPHOUS ALUMINUM OXIDE ON A CAPACITOR SIDEWALL FOR USE AS A HYDROGEN BARRIER

• US 20040099893A1
• Filed: 11/25/2002
• Published: 05/27/2004
• Est. Priority Date: 11/25/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Taylor, Kelly J., Summerfelt, Scott R., Colombo, Luigi, Moise, Theodore S., Hall, Lindsey, Martin, J. Scott, Aggarwal, Sanjeev, Udayakumar, K. R., Kuchimanchi, Sirisha
• Granted Patent: US 6,876,021 B2
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.

Claims

1. A ferroelectric device comprising:

a ferroelectric capacitor comprising;

a bottom electrode;

a ferroelectric layer formed on the bottom electrode;

a top electrode formed on the ferroelectric layer; and

a sidewall diffusion barrier layer formed at least on sidewalls of the ferroelectric capacitor, the sidewall diffusion barrier layer being comprised of amorphous aluminum oxide formed via a physical vapor deposition process.

2. The device of claim 1, wherein the sidewall diffusion barrier layer is formed at a low temperature.

3. The device of claim 2, wherein the low temperature is less than about 300°

C.

4. The device of claim 2, wherein the low temperature is about 180°

C.

5. The device of claim 1, wherein the sidewall diffusion barrier layer fully encapsulates the ferroelectric capacitor.

6. The device of claim 1, wherein the sidewall diffusion barrier layer has less than a predetermined number of crystalline features identifiable via a transmission electron microscope.

7. The device of claim 1, wherein the sidewall diffusion barrier layer substantially mitigates hydrogen contamination of the ferroelectric.

8. The device of claim 1, wherein the ferroelectric layer is comprised of Pb(Zr,Ti)O₃ (PZT).

9. The device of claim 1, wherein the sidewall diffusion barrier layer is about 200 Angstroms thick.

10. The device of claim 1, wherein the sidewall diffusion barrier layer is greater than about 400 Angstroms thick.

11. A method of fabricating a ferroelectric device comprising:

forming a bottom electrode;

forming a ferroelectric layer on the bottom electrode;

forming a top electrode on the ferroelectric layer;

selectively etching the bottom electrode, the ferroelectric layer and the top electrode, thereby defining a capacitor stack; and

performing a low temperature physical vapor deposition process to form an amorphous sidewall diffusion barrier layer along at least sidewalls of the capacitor stack.

12. The method of claim 11, wherein the sidewall diffusion barrier layer is formed so as to substantially encapsulate the capacitor stack.

13. The method of claim 11, wherein performing the low temperature physical vapor deposition process comprises sputtering an aluminum target with an argon gas in an oxygen containing environment to form the sidewall diffusion barrier layer.

14. The method of claim 11, wherein performing the low temperature physical vapor deposition process comprises forming an amorphous aluminum oxide layer along at least sidewalls of the capacitor stack.

15. A method of fabricating a ferroelectric device comprising:

forming a transistor in a semiconductor substrate;

forming an interlayer dielectric layer over the transistor;

forming a conductive contact in the dielectric layer down to a portion of the transistor;

forming a bottom electrode diffusion barrier layer over the interlayer dielectric layer;

forming a bottom electrode layer, a ferroelectric layer, a top electrode layer, and a hard mask over the bottom electrode diffusion barrier layer;

patterning the hard mask layer;

selectively etching the top electrode layer, the ferroelectric layer, and the bottom electrode layer using the hard mask to define a capacitor stack; and

performing a low temperature physical vapor deposition process to form a sidewall diffusion barrier layer comprised of amorphous aluminum oxide at least along sidewalls of the capacitor stack.

16. The method of claim 15, further comprising forming an interlevel dielectric layer over the sidewall diffusion barrier layer.

17. The method of claim 16, further comprising etching the interlevel dielectric layer to form contact holes and vias and forming interconnects in the contact holes and the vias.

18. A method of identifying hydrogen diffusion characteristics of a sidewall diffusion barrier layer, the method comprising:

forming a ferroelectric capacitor;

evaluating one or more initial electrical properties of the ferroelectric capacitor;

forming a sidewall diffusion barrier layer via a physical vapor deposition process, the sidewall diffusion barrier layer encapsulating the ferroelectric capacitor;

after forming the sidewall diffusion barrier layer, subjecting the ferroelectric capacitor stack to a hydrogen source; and

re-evaluating the one or more final electrical properties of the ferroelectric capacitor and determining hydrogen diffusion characteristics of the sidewall diffusion barrier layer from the initial electrical properties and the final electrical properties.

19. The method of claim 18, further comprising determining polarization retained by the ferroelectric capacitor from the initial and final electrical properties.

20. The method of claim 18, further comprising removing the sidewall diffusion barrier layer prior to re-measuring the final electrical properties.

21. The method of claim 18, wherein the sidewall diffusion barrier layer formed is comprised of amorphous aluminum oxide.

22. The method of claim 18, further comprising determining amorphousnous of the sidewall diffusion barrier layer by analyzing the sidewall diffusion barrier layer with a transmission electron microscope.

23. A method of selecting sidewall diffusion barrier layer processing parameters comprising:

selecting a unique set of sidewall processing parameters for each of a plurality of ferroelectric capacitors;

forming a unique sidewall diffusion barrier layer on each of the plurality of ferroelectric capacitors via a low temperature physical vapor deposition process according to the sets of sidewall processing parameters;

subjecting the plurality of ferroelectric capacitors to hydrogen contamination;

evaluating performance characteristics for each of the plurality of ferroelectric capacitors; and

selecting one of the sets of processing parameters based on the evaluation.

24. The method of claim 23, wherein evaluating performance comprises determining polarization retention for each of the plurality of ferroelectric capacitors.

25. The method of claim 24, wherein determining polarization retention comprises obtaining electrical properties of the plurality of ferroelectric capacitors and comparing them to initial electrical properties prior to the plurality of ferroelectric capacitors being subjected to the hydrogen contamination.

26. The method of claim 23, wherein the set of sidewall processing parameters respectively include temperature, argon gas flow, and duration.

27. The method of claim 23, further comprising forming a ferroelectric device, the ferroelectric device comprising a sidewall diffusion barrier layer formed according to the one selected set of processing parameters.

28. The method of claim 23, wherein the sidewall diffusion barrier layer comprises aluminum oxide and is associated with an aluminum oxide having a unique degree of amorphousness.