Memory device capable of stable data writing
First Claim
1. A memory device comprising:
- a memory cell array in which a plurality of memory cells are arranged through each of which a pass current when data is read flows at a value different according to a level of data written according to an applied data write current, said memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing; and
a plurality of current supply sections provided correspondingly to said plurality of regions, respectively, each of said plurality of current supply sections, when a corresponding region of said plurality of regions is selected as said object for data writing, being activated to supply said data write current to said corresponding region, wherein each of said plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of said plurality of memory cells, said plurality of write select lines being selectively supplied with said data write current from a corresponding one of said plurality of current supply sections.
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Accused Products
Abstract
A memory device according to the present invention includes a memory cell array including a plurality of memory cells arranged therein, the memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing, and further includes a plurality of current supply sections provided correspondingly to the plurality of regions, respectively. Each of the plurality of current supply sections, when a corresponding region of the plurality of regions is selected as an object for data writing, is activated to supply a data write current to the corresponding region and each of the plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of the plurality of memory cells. The plurality of write select lines are selectively supplied with the data write current from a corresponding one of the plurality of current supply sections.
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Citations
18 Claims
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1. A memory device comprising:
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a memory cell array in which a plurality of memory cells are arranged through each of which a pass current when data is read flows at a value different according to a level of data written according to an applied data write current, said memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing; and
a plurality of current supply sections provided correspondingly to said plurality of regions, respectively, each of said plurality of current supply sections, when a corresponding region of said plurality of regions is selected as said object for data writing, being activated to supply said data write current to said corresponding region, wherein each of said plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of said plurality of memory cells, said plurality of write select lines being selectively supplied with said data write current from a corresponding one of said plurality of current supply sections. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory device comprising:
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a plurality of memory cells through each of which a pass current when data is read flows at a value different according to a level of data written according to an applied data write current;
a plurality of write select lines provided correspondingly to predetermined units of said plurality of memory cells;
a current supply line connected electrically to said plurality of write select lines;
a plurality of current supply circuits, in data writing, supplying said data write current to said current supply line; and
a ground wire for, in said data writing, guiding said data write current supplied to said current supply line to at least one of a plurality of ground nodes through at least one of said plurality of write select lines, wherein said plurality of current supply circuits and said plurality of ground nodes are arranged so that path lengths, from said current supply line to said ground wire, respectively through write select lines corresponding to respective selected memory cells of said plurality of memory cells corresponding to respective input addresses are almost equal to each other regardless of a location of said selected memory cell. - View Dependent Claims (11, 12, 13, 14)
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15. A memory device comprising:
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a plurality of memory cells through each of which a pass current when data is read flows at a value different according to a level of data written according to an applied data write current;
a plurality of write select lines provided correspondingly to predetermined units of said plurality of memory cells;
a current supply line connected electrically to said plurality of write select lines;
a current supply circuit, in data writing, activated to connect said current supply line electrically to a first power supply voltage and to thereby supply said data write current to said current supply line;
an address decode circuit, receiving supply of a second power supply voltage to operate and to decode an input address, and for, in said data writing, selecting a write select line to receive supply of said data write current from said plurality of write select lines; and
a voltage detecting circuit, connected electrically to said second power supply voltage, and for detecting whether or not said address decode circuit has been activated based on a level of said second power supply voltage, and said current supply circuit includes a switch for disconnecting said current supply line electrically from said first power supply voltage according to a result of the detection of said voltage detecting circuit when said address decode circuit is in an inactive state, and a voltage level supplied by said first power supply voltage is higher than that supplied by said second power supply voltage. - View Dependent Claims (16, 17, 18)
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Specification