Memory device capable of stable data writing

• US 20040100819A1
• Filed: 05/19/2003
• Published: 05/27/2004
• Est. Priority Date: 11/27/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Hidaka, Hideto
• Granted Patent: US 6,898,114 B2
• Time in Patent Office: Days
• US Class Current: 365/173
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence

Abstract

A memory device according to the present invention includes a memory cell array including a plurality of memory cells arranged therein, the memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing, and further includes a plurality of current supply sections provided correspondingly to the plurality of regions, respectively. Each of the plurality of current supply sections, when a corresponding region of the plurality of regions is selected as an object for data writing, is activated to supply a data write current to the corresponding region and each of the plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of the plurality of memory cells. The plurality of write select lines are selectively supplied with the data write current from a corresponding one of the plurality of current supply sections.

Claims

1. A memory device comprising:

a memory cell array in which a plurality of memory cells are arranged through each of which a pass current when data is read flows at a value different according to a level of data written according to an applied data write current,

said memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing; and

a plurality of current supply sections provided correspondingly to said plurality of regions, respectively,

each of said plurality of current supply sections, when a corresponding region of said plurality of regions is selected as said object for data writing, being activated to supply said data write current to said corresponding region, wherein

each of said plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of said plurality of memory cells, said plurality of write select lines being selectively supplied with said data write current from a corresponding one of said plurality of current supply sections.

2. The memory device according to claim 1, wherein

each of said plurality of regions is divided into a plurality of blocks,

said plurality of blocks each include write select lines of said plurality of write select lines,

said memory cell array further includes a plurality of current supply lines provided correspondingly to said plurality of blocks respectively and each electrically connected to corresponding write select lines in corresponding one of said plurality of blocks, and

each of said current supply sections includes:

at least one current supply circuit supplying said data write current in said data writing; and

a power supply wire connecting each of said current supply lines in a corresponding region electrically to said current supply circuit.

3. The memory device according to claim 2, wherein

said power supply wire is provided so that respective path lengths between said current supply circuit and said plurality of current supply lines in a region corresponding to said current supply circuit are almost equal to each other.

4. The memory device according to claim 2, wherein

a plurality of said current supply circuits are provided

said plurality of current supply circuits are connected to said power supply wire, and

said plurality of current supply circuits are activated when a corresponding region of said plurality of regions is selected as said object for data writing to supply said data write current to a current supply line corresponding to each of said blocks in said corresponding region.

5. The memory device according to claim 2, wherein

each of said blocks further includes a ground wire for, in said data writing, guiding said data write current supplied to corresponding one of said current supply lines to a ground node through at least one of said plurality of write select lines, and

said current supply circuit and said ground node are arranged so that a path length of said data write current along said current supply line, a write select line corresponding to a selected memory cell of said plurality of memory cells corresponding to an input address and said ground wire is almost constant regardless of a location of said selected memory cell.

6. The memory device according to claim 2, wherein

each of said current supply sections further includes a decoupling capacitance provided between a power supply node receiving supply of an operating power supply voltage of said current supply circuit, and a ground voltage.

7. The memory device according to claim 2, wherein

said plurality of write select lines are provided correspondingly to memory cell rows, respectively.

8. The memory device according to claim 2, wherein

said plurality of write select lines are provided correspondingly to memory cell columns, respectively, to cause a current in a direction corresponding to write data to flow in a selected column.

9. The memory device according to claim 1, wherein

each of said plurality of memory cells includes:

a first magnetic layer having a fixed magnetic direction;

a second magnetic layer magnetized in a direction corresponding to a magnetic field generated by said data write current controlled according to a level of write data; and

an insulating film formed between said first and second magnetic layers.

10. A memory device comprising:

a plurality of memory cells through each of which a pass current when data is read flows at a value different according to a level of data written according to an applied data write current;

a plurality of write select lines provided correspondingly to predetermined units of said plurality of memory cells;

a current supply line connected electrically to said plurality of write select lines;

a plurality of current supply circuits, in data writing, supplying said data write current to said current supply line; and

a ground wire for, in said data writing, guiding said data write current supplied to said current supply line to at least one of a plurality of ground nodes through at least one of said plurality of write select lines, wherein

said plurality of current supply circuits and said plurality of ground nodes are arranged so that path lengths, from said current supply line to said ground wire, respectively through write select lines corresponding to respective selected memory cells of said plurality of memory cells corresponding to respective input addresses are almost equal to each other regardless of a location of said selected memory cell.

11. The memory device according to claim 10, further comprising:

decoupling capacitances provided between power supply nodes receiving supply of an operating power supply voltage of each of said current supply circuits and a ground voltage, respectively.

12. The memory device according to claim 10, wherein

said plurality of write select lines are provided correspondingly to memory cell columns, respectively.

13. The memory device according to claim 10, wherein

said plurality of write select lines are provided correspondingly to memory cell columns, respectively, to cause a current in a direction corresponding to write data to flow in a selected column.

14. The memory device according to claim 10, wherein

each of said plurality of memory cells includes:

a first magnetic layer having a fixed magnetic direction;

a second magnetic layer magnetized in a direction corresponding to a magnetic field generated by said data write current controlled according to a level of write data; and

an insulating film formed between said first and second magnetic layers.

15. A memory device comprising:

a plurality of memory cells through each of which a pass current when data is read flows at a value different according to a level of data written according to an applied data write current;

a plurality of write select lines provided correspondingly to predetermined units of said plurality of memory cells;

a current supply line connected electrically to said plurality of write select lines;

a current supply circuit, in data writing, activated to connect said current supply line electrically to a first power supply voltage and to thereby supply said data write current to said current supply line;

an address decode circuit, receiving supply of a second power supply voltage to operate and to decode an input address, and for, in said data writing, selecting a write select line to receive supply of said data write current from said plurality of write select lines; and

a voltage detecting circuit, connected electrically to said second power supply voltage, and for detecting whether or not said address decode circuit has been activated based on a level of said second power supply voltage, and

said current supply circuit includes a switch for disconnecting said current supply line electrically from said first power supply voltage according to a result of the detection of said voltage detecting circuit when said address decode circuit is in an inactive state, and

a voltage level supplied by said first power supply voltage is higher than that supplied by said second power supply voltage.

16. The memory device according to claim 15, wherein

said voltage detecting circuit detects whether said address decode circuit is active or inactive according to whether or not said second power supply voltage exceeds a predetermined level.

17. The memory device according to claim 15, wherein

said data writing is activated by an external control signal,

the memory device further comprises:

a period control circuit for limiting a period during which said current supply line is connected electrically to said first power supply voltage to a predetermined period when said data writing is activated by said control signal.

18. The memory device according to claim 15, wherein

each of said plurality of memory cells includes:

a first magnetic layer having a fixed magnetic direction;

a second magnetic layer magnetized in a direction corresponding to a magnetic field generated by said data write current controlled according to a level of write data; and

an insulating film formed between said first and second magnetic layers.