Serial ATA frame structure routing circuitry and protocols

• US 20040100944A1
• Filed: 11/27/2002
• Published: 05/27/2004
• Est. Priority Date: 11/27/2002
• Status: Abandoned Application

• Current Assignee: APT Technologies, Inc. (Microchip Technology Incorporated)
• Original Assignee: APT Technologies, Inc. (Microchip Technology Incorporated)
• Inventors: Rubino, James, Deyring, Klaus-Peter, Woodral, David Eugene, Palumbo, Frank Salvatore, Richmond, Scott
• Application Number:
  US10/306,350
• Publication Number:
  US 20040100944A1
• Time in Patent Office: Days
• US Class Current: 370/360
• CPC Class Codes: H04L 45/02 Topology update or discovery
• CPC Class Codes: H04L 45/306 Route determination based on the nature of the carried application
• CPC Class Codes: H04L 45/34 Source routing
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 49/35 Switches specially adapted for specific applications

Abstract

A topology and devices and protocols comprising a switched fabric which allow attaching multiple mass storage devices through said switched fabric over any serial point to point mass storage interface. This switched fabric interface uses one or more point to point serial interfaces, such as Serial ATA to provide the connectivity of multiple drives to one or more ports on a server or PC class computer and includes routers which use router headers in FIS to establish routes and guide data. Disclosed are the switch concept, switch ASIC devices, and switch firmware in a switch supporting any number of host connections and number of drive connections. The protocols disclosed also provide the ability to connect multiple hosts to a bank of switch mass storage devices. The processes disclosed includes protocol conversions from Serial ATA 2.xx to Serial ATA 1.xx devices. A smart FIFO is disclosed which saves memory by the removal of unused primitives from the input stream, and conditionally re-inserting them into the output stream.

Claims

1. A switchable fabric interface using one or more connections over a point to point, serial topology, mass storage interface, such as Serial ATA, that allows for the connection of multiple mass storages devices to one or morehost devices such as file servers, application servers, individual computers, workstations, network attach storage devices, and protocol bridge devices to form a storage area network using serial, point to point protoco

2. A collision resolution protocol in a serial ATA topology that has more than two devices coupled together by serial ATA links, comprising the steps carried out in a node at the collision site:

receiving at a first node coupled to a data path on which a collision will occur a primitive from a second node that indicates said second node desires to transmit a data packet with a header that includes routing data to said first node, and responding thereto by sending back a primitive that gives permission to said second node to send only said header of said data packet;

receiving at a third node coupled to a data path on which a collision will occur a primitive from a fourth node indicating said fourth node desires to transmit a data packet with a header that includes routing data to said third node, and responding thereto by sending back a primitive that gives permission to said fourth node to send only said header of said data packet;

reading the routing data in the headers and concluding a collision will occur;

deciding which initiator node will have to back off and listen in any way;

sending a message to the losing initiator node telling it that it will have to listen; and

completing the transaction by sending data to the losing initiator node.

3. A protocol conversion protocol, comprising the steps:

receiving from a serial ATA 2.xx initiator node serial ATA 2.xx primitives or serial ATA 2.xx FIS having a prepended route header field which defines a route directed to a serial ATA 1.xx device which has no route awareness capability;

converting said serial ATA 2.xx primitives received from said serial ATA 2.xx initiator node to serial ATA 1.xx primitives and forwarding said serial ATA 1.xx primitives to said serial ATA 1.xx device;

receiving any serial ATA 1.xx primitives back from said serial ATA 1.xx device, and forwarding said serial ATA 1.xx primitives to said serial ATA 2.xx initiator node;

receiving serial ATA 2.xx data FIS with appended route header from said serial ATA 2.xx initator node in response to receipt by said serial ATA 2.xx initiator node of said serial ATA 1.xx primitive from said serial ATA 1.xx device;

stripping off the route header field and any other fields or primitives in said serial ATA 2.xx data FIS which said serial ATA 1.xx device will not understand, and forwarding the remainder of said FIS to said serial ATA 1.xx device, and storing said route header of said serial ATA 2.xx data FIS which was stripped therefrom;

receiving from said serial ATA 1.xx device a serial ATA 1.xx primitive that terminates said transaction and forwarding said serial ATA 1.xx primitive to the serial ATA 2.xx initiator node identified in said stored router header to close the connection between said serial ATA 2.xx initiator node and said serial ATA 1.xx device.

4. A process for routing in serial ATA systems, comprising:

receiving a serial ATA 2.xx route header or a serial ATA 2.xx router header which is part of a serial ATA 2.xx FIS, and using routing information therein to route the header or the entire serial ATA 2.xx FIS to a destination device; and

as said serial aTA 2.xx route header is passed through a serial ATA 2.xx topology, altering the routing data in said route header to point to the reverse path.

5. A router and buffer for a serial ATA topology that allows more than one host and storage device to be coupled together by serial ATA buses, comprising:

a plurality of ports, each for coupling to a serial ATA bus;

a crossbar switch coupled to each port;

a port specific data structure coupled to each port;

and wherein each port comprises;

circuitry for reading route data in a header of an incoming FIS and controlling said crossbar switch to make the appropriate connections between ports in said router to implement a connection defined in the route data of said header;

circuitry for altering said route data in a header of an incoming FIS to define reverse route header data;

circuitry to receive a FIS back from the destination node defined by said route data for a forward route which contains a data element which defines the FIS as a reverse route FIS and recognize that said FIS is a reverse route FIS and use said reverse route header data to route said reverse route FIS.

6. The apparatus of claim 5 wherein each port further comprising means for detecting and resolving collisions using a header transmission only protocol.

7. The apparatus of claim 5 wherein each port further comprises means for detecting when a serial ATA 1.xx device which is not route aware is coupled to a port and for performing appropriate protocol conversions to allows said serial ATA 1.xx device to communicate with other serial ATA 2.xx devices in the topology in which said router and buffer will be connected.

8. The apparatus of claim 5 wherein said buffer includes means for removing primitives and data deemed unnecessary from the incoming data before storage in a FIFO organized memory, and for regenerating or duplicating at the output of said FIFO the removed primitives or data at least enough to not alter the functionality of the output data stream.

9. The apparatus of claim 5 wherein said circuitry to alter said route data to define the reverse path does not lock the ports for a forward or reverse route defined by said route data.

10. A computer readable memory having stored thereon a data structure comprising:

1) an RTX primitive;

2) a separator data item which separates said route data header from said RTX primitive;

3) a route data header;

4) a field of error detection and correction data calculated on data items 1 through 3;

5) a payload data section;

6) a field of error detection and correction data calculated on said payload data section;

7) a separator data item that separates fields 6 and 8.

8) a WTRM primitive; and