Digital receiver capable of processing modulated signals at various data rates

• US 20040101068A1
• Filed: 11/25/2002
• Published: 05/27/2004
• Est. Priority Date: 11/25/2002
• Status: Active Grant

• Current Assignee: Ali SPA (Bessemer Group Incorporated)
• Original Assignee: Ali SPA (Bessemer Group Incorporated)
• Inventors: Lee, Chun-Hsien, Wang, Tzu-Pai
• Granted Patent: US 7,180,963 B2
• Time in Patent Office: Days
• US Class Current: 375/324
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 1/7105 Joint detection techniques, e.g. linear detectors
• CPC Class Codes: H04B 2201/70703 using multiple or variable rates
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2027/003 at baseband only
• CPC Class Codes: H04L 2027/0055 single phase
• CPC Class Codes: H04L 25/0212 of impulse response
• CPC Class Codes: H04L 25/0224 using sounding signals
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

A digital receiver is enabled to process modulated signals at various data rates including a sampling circuit for receiving modulated signals and outputting digitalized sampled signals, a matched filter for expelling noise from digitalized sampled signals at a first data rate and at a second data rate and generating in-phase and quadrature-phase signals, a barker code correlator for depreading digitalized sampled signals at first data rate, a channel equalizer which counteracts co-channel interferences by using equalizer coefficients obtained from a plurality of noise whitening coefficients so as to generate a sequence of symbol decisions therefrom, a CCK correlator coupled to the channel equalizer for decoding signals at the second data rate and at a third data rate, a first quantization filter for recovering transmitted signals at the first data rate, and a second quantization fitler for recovering transmitted signals at the second data rate and at the third data rate.

Claims

1. A digital receiver configured to process modulated signals at various data rates, comprising:

a sampling circuit operating at a fixed sampling rate for receiving transmitted signals and outputting digitalized sampled signals;

a channel matched filter for expelling noise from the digitalized sampled signal at a first data rate and at a second data rate and generating in-phase and quadrature-phase signals;

a first correlator unit coupled to the channel matched filter for depreading the digitalized sampled signal at the first data rate;

a channel equalizer which counteracts co-channel interferences by using equalizer coefficients obtained from a plurality of noise whitening coefficients so as to generate a sequence of symbol decisions therefrom;

a second correlator unit coupled to the channel equalizer for decoding signals at the second data rate and at a third data rate;

a first quantization filter for recovering transmitted signals at the first data rate; and

a second quantization fitler for recovering transmitted signals at the second data rate and at the third data rate.

2. The digital receiver according to claim 1 wherein the sampling circuit comprises an analog-to-digital converter.

3. The digital receiver according to claim 1 further comprising:

an interpolator coupled to the sampling circuit for adjusting a sampling frequency offset of the digitalized sampled signals generated by the sampling circuit by interpolating the digitalized sampled signals according to an interpolation coefficient; and

a derotator coupled to the interpolator for compensating a carrier phase offset according to a phase-adjusting signal.

4. The digital receiver according to claim 3 further comprising:

a timing recovery loop for calculating a sampling frequency offset and a sampling phase offset to control an interpolation of the interpolator; and

a carrier recovery loop for locking on a carrier phase offset and in response thereto generating the phase-adjusting signal.

5. The digital receiver according to claim 4 wherein the timing recovery loop comprises:

a frequency detector configured to receive the digitalized sampled signals and output an instantaneous symbol timing error signal;

a loop filter for receiving the instantaneous symbol timing error signal and calculating an average symbol timing error signal;

a numerically-controlled oscillator for providing the interpolator with the interpolation coefficients based on the average symbol timing error signal;

a timing frequency locking circuit which ties a frequency of an oscillator within the digital receiver to a frequency of an oscillator within a transmitter; and

a timing acquisition loop for receiving the digitalized sampled signals and generating a bit timing estimate.

6. The digital receiver according to claim 4 wherein the carrier recovery loop comprises:

a phase detector configured to generate an instantaneous carrier phase error signal based on the in-phase and quadrature-phase signals; and

a loop filter configured to calculate an average phase error signal and generating the phase-adjusting signal based on the average phase error signal.

7. The digital receiver according to claim 1 wherein the channel equalizer comprises a decision feedback equalizer.

8. The digital receiver according to claim 1 wherein the first correlator unit comprises a barker code correlator which uses a barker code of 11 chips to despread the digitalized sampled signal at the first data rate.

9. The digital receiver according to claim 1 wherein the second correlator unit comprises a CCK correlator which performs a maximum likelihood decoding process to the digitalized sampled signals at the second data rate and at the third data rate.

10. The digital receiver according to claim 1 wherein the first quantization filter comprises:

a first slicer which quantizes digitalized sampled signals at the first date rate according to a reference slice signal to produce digital symbols; and

a first differential decoder coupled to the first slicer for removing a phase ambiguity of the digital symbols.

11. The digital receiver according to claim 1 wherein the second quantization filter comprises:

a peak selector which outputs largest outputs of the second corrrlator unit as parallel digital samples;

a second slicer which quantizes the parallel digital samples at the second data rate and at the third date rate according to a reference slice signal to produce parallel digital symbols;

a second differential decoder which removes a phase ambiguity from the parallel digital symbols; and

a parallel in-serial-out shift register for converting the parallel digital symbols into serial digital symbols.

12. The digital receiver according to claim 1 further comprising:

a descrambler coupled to the first quantization filter and the second qualization filter for subtracting a pseudo noise sequence from digital symbols; and

a cyclic redundancy check (CRC) checker configured to detect an error within a header of a data packet.

13. The digital receiver according to claim 1 wherein the first data rate is 1 Mbps or 2 Mbps.

14. The digital receiver according to claim 1 wherein the second data rate is 5.5 Mbps and the third data rate is 11 Mbps.

15. A digital receiver for processing modulated data signals at various data rates, comprising:

a sampling circuit operating at a fixed sampling rate for receiving transmitted signals and outputting digitalized sampled signals;

a derotator for compensating a carrier phase offset according to a phase-adjusting signal.

a channel matched filter for expelling noise from the digitalized sampled signal and generating in-phase and quadrature-phase signals;

a first correlator unit coupled to the channel matched filter for depreading the digitalized sampled signal;

a channel equalizer which counteracts co-channel interferences by using equalization coefficients obtained from a plurality of noise whitening coefficients so as to generate a sequence of symbol decisions therefrom;

a second correlator unit coupled to the channel equalizer for decoding modulated signals;

a first quantization filter; and

a second quantization fitler;

wherein a received signal at a first data rate is processed through a first signal processing path constituted by the sampling circuit, the derotator, the channel matched filter, the first correlator unit and the first quantization filter, a received signal at a second date rate is processed through a second signal processing path constituted by the sampling circuit, the derotator, the channel matched filter, the second correlator unit and the second quantization filter, and a received signal at a third date rate is processed through a third signal processing path constituted by the sampling circuit, the derotator, the channel equalizer, the second correlator unit and the second quantization filter.

16. The digital receiver according to claim 15 wherein the sampling circuit comprises an analog-to-digital converter.

17. The digital receiver according to claim 15 further comprising an interpolator coupled to the sampling circuit for adjusting a sampling frequency offset of the digitalized sampled signals generated by the sampling circuit by interpolating the digitalized sampled signals according to an interpolation coefficient.

18. The digital receiver according to claim 17 further comprising:

a timing recovery loop for calculating a sampling frequency offset and a sampling phase offset to control an interpolation of the interpolator; and

a carrier recovery loop for locking on a carrier phase offset and in response thereto generating the phase-adjusting signal.

19. The digital receiver according to claim 18 wherein the timing recovery loop comprises:

a frequency detector configured to receive the digitalized sampled signals and output an instantaneous symbol timing error signal;

a loop filter for receiving the instantaneous symbol timing error signal and calculating an average symbol timing error signal;

a numerically-controlled oscillator for providing the interpolator with the interpolation coefficients based on the average symbol timing error signal;

a timing frequency locking circuit which ties a frequency of an oscillator within the digital receiver to a frequency of an oscillator within a transmitter; and

a timing acquisition loop for receiving the digitalized sampled signals and generating a bit timing estimate.

20. The digital receiver according to claim 18 wherein the carrier recovery loop comprises:

a phase detector configured to generate an instantaneous carrier phase error signal based on the in-phase and quadrature-phase signals; and

a loop filter configured to calculate an average phase error signal and generating the phase-adjusting signal based on the average phase error signal.

21. The digital receiver according to claim 15 wherein the channel equalizer comprises a decision feedback equalizer.

22. The digital receiver according to claim 15 wherein the first correlator unit comprises a barker code correlator which uses a barker code of 11 chips to despread the digitalized sampled signal at the first data rate.

23. The digital receiver according to claim 15 wherein the second correlator unit comprises a CCK correlator which performs a maximum likelihood decoding process to the digitalized sampled signals at the second data rate and at the third data rate.

24. The digital receiver according to claim 15 wherein the first quantization filter comprises:

a first slicer which quantizes digitalized sampled signals at the first date rate according to a reference slice signal to produce digital symbols; and

a first differential decoder coupled to the first slicer for removing a phase ambiguity of the digital symbols.

25. The digital receiver according to claim 15 wherein the second quantization filter comprises:

a peak selector which outputs largest outputs of the second corrrlator unit as parallel digital samples;

a second slicer which quantizes the parallel digital samples at the second data rate and at the third date rate according to a reference slice signal to produce parallel digital symbols;

a second differential decoder which removes a phase ambiguity from the parallel digital symbols; and

a parallel-in-serial-out shift register for converting the parallel digital symbols into serial digital symbols.

26. The digital receiver according to claim 15 further comprising:

a descrambler coupled to the first quantization filter and the second qualization filter for subtracting a pseudo noise sequence from digital symbols; and

a cyclic redundancy check (CRC) checker configured to detect an error within a header of a data packet.

27. The digital receiver according to claim 15 wherein the first data rate is 1 Mbps or 2 Mbps.

28. The digital receiver according to claim 15 wherein the second data rate is 5.5 Mbps and the third data rate is 11 Mbps.

29. A digital receiver for processing modulated data signals at various data rates, comprising:

a sampling circuit operating at a fixed sampling rate for receiving transmitted signals and outputting digitalized sampled signals;

an interpolator coupled to the sampling circuit for adjusting a sampling frequency offset of the digitalized sampled signals generated by the sampling circuit by interpolating the digitalized sampled signals according to an interpolation coefficient;

a derotator coupled to the interpolator for compensating a carrier phase offset according to a phase-adjusting signal;

a timing recovery loop for calculating a sampling frequency offset and a sampling phase offset to control an interpolation of the interpolator;

a carrier recovery loop for locking on a carrier phase offset and in response thereto generating the phase-adjusting signal;

a channel matched filter for expelling noise from the digitalized sampled signal and generating in-phase and quadrature-phase signals;

a first correlator unit coupled to the channel matched filter for depreading the digitalized sampled signal;

a channel equalizer which counteracts co-channel interferences by using equalization coefficients obtained from a plurality of noise whitening coefficients so as to generate a sequence of symbol decisions therefrom;

a second correlator unit coupled to the channel equalizer for decoding modulated signals;

a first quantization filter; and

a second quantization fitler;

wherein a received signal at a first data rate is processed through a first signal processing path constituted by the sampling circuit, the derotator, the channel matched filter, the first correlator unit and the first quantization filter, a received signal at a second date rate is processed through a second signal processing path constituted by the sampling circuit, the derotator, the channel matched filter, the second correlator unit and the second quantization filter, and a received signal at a third date rate is processed through a third signal processing path constituted by the sampling circuit, the derotator, the channel equalizer, the second correlator unit and the second quantization filter.

30. The digital receiver according to claim 29 wherein the sampling circuit comprises an analog-to-digital converter.

31. The digital receiver according to claim 29 wherein the timing recovery loop comprises:

a frequency detector configured to receive the digitalized sampled signals and output an instantaneous symbol timing error signal;

a loop filter for receiving the instantaneous symbol timing error signal and calculating an average symbol timing error signal;

a numerically-controlled oscillator for providing the interpolator with the interpolation coefficients based on the average symbol timing error signal;

a timing frequency locking circuit which ties a frequency of an oscillator within the digital receiver to a frequency of an oscillator within a transmitter; and

a timing acquisition loop for receiving the digitalized sampled signals and generating a bit timing estimate.

32. The digital receiver according to claim 29 wherein the carrier recovery loop comprises:

a phase detector configured to generate an instantaneous carrier phase error signal based on the in-phase and quadrature-phase signals; and

a loop filter configured to calculate an average phase error signal and generating the phase-adjusting signal based on the average phase error signal.

33. The digital receiver according to claim 29 wherein the channel equalizer comprises a decision feedback equalizer.

34. The digital receiver according to claim 29 wherein the first correlator unit comprises a barker code correlator which uses a barker code of 11 chips to despread the digitalized sampled signal at the first data rate.

35. The digital receiver according to claim 29 wherein the second correlator unit comprises a CCK correlator which performs a maximum likelihood decoding process to the digitalized sampled signals at the second data rate and at the third data rate.

36. The digital receiver according to claim 29 wherein the first quantization filter comprises:

a first slicer which quantizes digitalized sampled signals at the first date rate according to a reference slice signal to produce digital symbols; and

a first differential decoder coupled to the first slicer for removing a phase ambiguity of the digital symbols.

37. The digital receiver according to claim 29 wherein the second quantization filter comprises:

a peak selector which outputs largest outputs of the second corrrlator unit as parallel digital samples;

a second slicer which quantizes the parallel digital samples at the second data rate and at the third date rate according to a reference slice signal to produce parallel digital symbols;

a second differential decoder which removes a phase ambiguity from the parallel digital symbols; and

a parallel-in-serial-out shift register for converting the parallel digital symbols into serial digital symbols.

38. The digital receiver according to claim 29 further comprising:

a descrambler coupled to the first quantization filter and the second qualization filter for subtracting a pseudo noise sequence from digital symbols; and

a cyclic redundancy check (CRC) checker configured to detect an error within a header of a data packet.

39. The digital receiver according to claim 29 wherein the first data rate is 1 Mbps or 2 Mbps.

40. The digital receiver according to claim 29 wherein the second data rate is 5.5 Mbps and the third data rate is 11 Mbps.