Equaliser apparatus and methods

• US 20040101072A1
• Filed: 08/15/2003
• Published: 05/27/2004
• Est. Priority Date: 08/16/2002
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Cepeda Lopez, Rafael Arcangel, Fitton, Michael Philip, Leong, Siew Chung, Gargin, Douglas John
• Granted Patent: US 7,330,505 B2
• Time in Patent Office: Days
• US Class Current: 375/341
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 25/0236 using estimation of the other symbols
• CPC Class Codes: H04L 25/03286 with channel-decoding circuitry
• CPC Class Codes: H04L 25/03292 with channel estimation circuitry

Abstract

This invention is generally concerned with equalisation in digital communications systems, and more particularly with improved methods and apparatus for MLSE (Maximum Likelihood Sequence Estimation) equalisation.

An equaliser (300) for a digital communications system is described. The equaliser comprises a first buffer (308) to store received data prior to equalisation; a second buffer (324) to store error-checked received data; a channel estimator (320) coupled to said first and second buffers to determine a channel estimate using said received data from said first buffer and said error-checked data from said second buffer; and a control unit (310) coupled to said channel estimator to update a channel estimate for use by said equaliser in equalising said received data.

Claims

1. An equaliser for a digital communications system, the equaliser comprising:

a first buffer to store received data prior to equalisation;

a second buffer to store error-checked received data;

a channel estimator coupled to said first and second buffers to determine a channel estimate using said received data from said first buffer and said error-checked data from said second buffer; and

a control unit coupled to said channel estimator to update a channel estimate for use by said equaliser in equalising said received data.

2. An equaliser as claimed in claim 1 wherein said control unit is configured to perform said updating conditional upon a difference between the channel estimate and a previous channel estimate used for equalising said received data.

3. An equaliser as claimed in claim 1 further comprising a look-up table coupled to said control unit and calculating means coupled to said look-up table to calculate and store in said look-up table, data for a plurality of symbol sequences, the data for each symbol sequence comprising data obtained by applying a said channel estimate to a sequence of symbols.

4. An equaliser as claimed in claim 3 further comprising a plurality of metric determining modules each coupled to said look-up table for determining in parallel, a plurality of metrics for comparing said received data and the data for said symbol sequences, whereby a symbol sequence for said received data may be selected.

5. An equaliser as claimed in claim 1 further configured to use said updated channel estimate to equalise previously received data determined to be erroneous.

6. An equaliser as claimed in claim 1 wherein said control unit is further configured to control the equaliser to disregard parameters of said channel estimate of less than a threshold significance.

7. An equaliser as claimed in claim 6 wherein said threshold significance is variable.

8. An equaliser as claimed in claim 1 wherein said error-checked data comprises error-corrected data.

9. An equaliser according to claim 1 of the MLSE type.

22. Processor control code to, when running, implement the equaliser or method of any preceding claim.

23. A carrier carrying the processor control code of claim 22.

10. A method of equalising data in a digital communication system, the method comprising:

receiving data for equalisation;

equalising said received data;

error-checking said equalised data;

determining a channel estimate using said received data and said error-checked equalised data; and

updating a channel estimate for use in said equalisation using said determined channel estimate.

11. A method as claimed in claim 10 further comprising:

storing said received data in a first buffer;

storing said error-checked data in a second buffer; and

reading data from said first and second buffers for said determining of said channel estimate.

12. A method as claimed in claim 10 wherein said updating is conditional upon said channel estimate being different from a channel estimate previously used for said equalising by more than an updating trigger level.

13. A method as claimed in claim 10 further comprising:

re-equalising previously received data following said updating.

14. A method as claimed in claim 10 further comprising:

modifying said channel estimate to reduce a computational load of said equaliser.

15. A method as claimed in claim 14 wherein said modifying comprises discarding parameters of said estimate of less than a threshold significance.

16. A method as claimed in claim 15 further comprising modifying said threshold significance, in particular in response to a desired power consumption.

17. A method as claimed in claim 10 further comprising:

storing said channel estimate in a look-up table as data for a plurality of symbol sequences modified by said channel estimate.

18. A method as claimed in claim 17 further comprising:

providing data from said look-up table to a plurality of metric determining modules for determining, in parallel, metrics for evaluating hypothesised symbol sequences against said received data, for estimating a symbol sequence of said received data.

19. A method as claimed in claim 10 wherein said equalising comprises MLSE-type equalising.

20. A method of MLSE type data equalisation in a digital communication system, the method comprising:

receiving data for equalisation;

selecting a first estimated sequence for a portion of the received data from a plurality of hypothesised symbol sequences according to a metric for determining the closeness of a hypothesised sequence to the portion of received data;

performing an error check procedure on the selected symbol sequence; and

selecting a second estimated symbol sequence in response to said error check determining that said first sequence is erroneous.

21. A method as claimed in claim 20 wherein said first sequence has a metric indicating that of the hypothesised sequences it is closest to the portion of received data, and wherein said second sequence has a metric indicating that of the hypothesised sequences it is next closest to the portion of received data.

24. An equaliser for a digital communications system, the equaliser comprising:

a channel estimator configured to derive and store a channel estimate from data received by the equaliser;

a control unit coupled to said channel estimator to update the stored channel estimate conditionally upon a change in said channel estimate of greater than a threshold level.

25. An equaliser as claimed in claim 24 further comprising:

a look-up table configured to store data relating to said channel estimate as data for a plurality of symbol sequences to which said channel estimate has been applied; and

wherein said control unit is further coupled to said look-up table to update the data in said look-up table conditionally upon a change in said channel estimate of greater than a threshold level.

26. An equaliser as claimed in claim 24 wherein said control unit is configured to control said equaliser to discard components of said channel estimate under a discard threshold level.

27. An equaliser as claimed in claim 26 wherein said discard threshold level is controllable.

28. An equaliser as claimed in claim 24 of the MLSE type.

29. A method of equalising data in a digital communications system, the method comprising:

receiving data for equalisation;

determining a channel estimate using said received data;

determining whether said channel estimate is significantly different from a previously used channel estimate;

storing said channel estimate conditionally upon said difference determining, and

equalising said received data using said stored data.

30. A method as claimed in claim 29 wherein said storing comprises storing said channel estimate in a look-up table as data relating to a plurality of symbol sequences to which said channel estimate has been applied, and wherein said equalising uses said data stored in said look-up table.

31. Processor control code to, when running, implement an equaliser for a digital communications system, the equaliser comprising:

a channel estimator configured to derive and store a channel estimate from data received by the equaliser;

a control unit coupled to said channel estimator to update the stored channel estimate conditionally upon a change in said channel estimate of greater than a threshold level.

32. Processor control code to, when running, implement a method of equalising data in a digital communications system, the method comprising:

receiving data for equalisation;

determining a channel estimate using said received data;

determining whether said channel estimate is significantly different from a previously used channel estimate;

storing said channel estimate conditionally upon said difference determining, and

equalising said received data using said stored data.

33. A carrier carrying processor control code to, when running, implement an equaliser for a digital communications system, the equaliser comprising:

a channel estimator configured to derive and store a channel estimate from data received by the equaliser;

a control unit coupled to said channel estimator to update the stored channel estimate conditionally upon a change in said channel estimate of greater than a threshold level.

34. A carrier carrying processor control code to, when running, implement a method of equalising data in a digital communications system, the method comprising:

receiving data for equalisation;

determining a channel estimate using said received data;

determining whether said channel estimate is significantly different from a previously used channel estimate;

storing said channel estimate conditionally upon said difference determining, and

equalising said received data using said stored data.

35. An equaliser for a digital communications system, the equaliser comprising:

a channel estimator configured to derive a channel estimate from data received by the equaliser;

a look-up table configured to store data relating to said channel estimate as data for a plurality of symbol sequences to which said channel estimate has been applied;

a plurality of metric determining modules each coupled to said look-up table, for determining a plurality of metrics in parallel, each metric for evaluating one of said symbol sequences against said received data; and

a controller to output a selected one of said symbol sequences.

36. Processor control code to, when running, implement an equaliser for a digital communications system, the equaliser comprising:

a channel estimator configured to derive a channel estimate from data received by the equaliser;

a look-up table configured to store data relating to said channel estimate as data for a plurality of symbol sequences to which said channel estimate has been applied;

a plurality of metric determining modules each coupled to said look-up table, for determining a plurality of metrics in parallel, each metric for evaluating one of said symbol sequences against said received data; and

a controller to output a selected one of said symbol sequences.

37. A carrier carrying processor control code to, when running, implement an equaliser for a digital communications system, the equaliser comprising:

a channel estimator configured to derive a channel estimate from data received by the equaliser;

a look-up table configured to store data relating to said channel estimate as data for a plurality of symbol sequences to which said channel estimate has been applied;

a plurality of metric determining modules each coupled to said look-up table, for determining a plurality of metrics in parallel, each metric for evaluating one of said symbol sequences against said received data; and

a controller to output a selected one of said symbol sequences.