Use of chromeless phase shift features to pattern large area line/space geometries
First Claim
12. A method for patterning a large area feature on a semiconductor substrate, comprising:
- providing a chromeless phase shift lithography (CPL) mask comprising a reticle having a plurality of phase-shifting features interspersed with non-phase-shifting areas, said phase-shifting features arranged in a substantially alternating two-dimensional pattern with non-phase shifting areas, said pattern substantially occupying an area on the CPL mask having a shape corresponding to the large area feature;
illuminating the CPL mask with a short wavelength light source, wherein light passing through the phase-shifting features is phase-shifted relative to light passing through the non-phase-shifted areas of the CPL mask; and
projecting phase-shifted and non-phase-shifted light passing through the CPL mask onto a layer of resist applied over the semiconductor substrate to expose an area on the resist corresponding to the large area feature.
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Accused Products
Abstract
Method for using chromeless phase shift lithography (CPL) masks to pattern large line/space geometries and corresponding CPL masks. The method comprises using a short wavelength light to illuminate a CPL mask comprising a reticle having a plurality of phase-shifting features interspersed with non-phase-arranged in a substantially alternating two-dimensional pattern. When light passes through the phase-shifting features it is phase-shifted relative to light passing through the non-phase-shifting areas of the CPL mask. The phase-shifted and non-phase-shifted light passing through the reticle is then projected onto a resist layer applied over a semiconductor substrate. The resultant composite aerial image intensity distribution is such that an area of the resist having a shape defined by a periphery of a corresponding pattern of phase-shifting features is sufficiently exposed to pattern a large area feature in the resist. Subsequent semiconductor processing operations may then be performed to pattern a corresponding feature in the semiconductor substrate.
13 Citations
27 Claims
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12. A method for patterning a large area feature on a semiconductor substrate, comprising:
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providing a chromeless phase shift lithography (CPL) mask comprising a reticle having a plurality of phase-shifting features interspersed with non-phase-shifting areas, said phase-shifting features arranged in a substantially alternating two-dimensional pattern with non-phase shifting areas, said pattern substantially occupying an area on the CPL mask having a shape corresponding to the large area feature;
illuminating the CPL mask with a short wavelength light source, wherein light passing through the phase-shifting features is phase-shifted relative to light passing through the non-phase-shifted areas of the CPL mask; and
projecting phase-shifted and non-phase-shifted light passing through the CPL mask onto a layer of resist applied over the semiconductor substrate to expose an area on the resist corresponding to the large area feature. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A chromeless phase shift lithography (CPL) mask comprising:
a reticle having a plurality of phase-shifting features formed therein, said plurality of phase-shifting features causing light passing therethough to be shifted approximately 180°
in phase relative to light passing through non-phase-shifting areas of the reticle not occupied by a phase-shifting feature, said phase-shifting features arranged in a substantially alternating two-dimensional pattern with the non-phase-shifting areas of the CPL mask to produce a projected aerial image to pattern one or more large resist areas on a semiconductor substrate.- View Dependent Claims (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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25-1. The CPL mask of claim 18, wherein reticle comprises quartz.
Specification