Linearization technique for phase locked loops employing differential charge pump circuitry

• US 20040102170A1
• Filed: 11/27/2002
• Published: 05/27/2004
• Est. Priority Date: 11/27/2002
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Jensen, Henrik T., Kappes, Michael
• Granted Patent: US 6,941,116 B2
• Time in Patent Office: Days
• US Class Current: 455/260
• CPC Class Codes: H01Q 1/246 specially adapted for base stations
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

A differential linear fractional N-synthesizer includes a phase and frequency detection module, a linearized charge pump, a low pass filter, a voltage controlled oscillator, and a fractional N divider feedback. The phase and frequency detection module is operably coupled to produce a differential charge-up signal, a differential charge-down signal, or a differential off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The feedback oscillation is generated by the fractional N divider feedback, which divides an output oscillation by a divider value to produce the feedback oscillation. The linearized charge pump includes a 1^st current source, a 2^nd current source and a modulation module. In response to the differential off signal, the modulation module produces a modulated differential off signal that causes the 1^st and 2^nd current sources to produce a zero current signal in an alternating fashion. The low pass filter is operably coupled to attenuate the high frequency signal components produced by the modulation module of the linearized charge pump and to pass the positive, negative or zero current signals to produce a filtered signal. The voltage control oscillator produces the output oscillation based on the filtered signal.

Claims

1. A differential linear phase locked loop comprises:

phase and frequency detection module operably coupled to produce a differential charge up signal, a differential charge down signal, or a differential off signal based on at least one of a phase difference between a reference oscillation and a feedback oscillation and a frequency difference between the reference oscillation and the feedback oscillation;

linearized charge pump operably coupled to produce a positive current signal in response to the differential charge up signal, a negative current signal in response to the differential charge down signal, and zero current signal in response to the differential off signal, wherein the linearized charge pump includes;

first current source module operably coupled to provide a first positive current in response to the differential charge up signal and to provide a first negative current in response to the differential charge down signal;

second current source module operably coupled to provide a second positive current in response to the differential charge up signal and to provide a second negative current in response to the differential charge down signal, wherein the first and second positive currents provide the positive current signal, wherein the first and second negative currents provide the negative current signal, and wherein the first current source module provides the first positive current and the second current source module provides the second negative current or the first current source module provides the first negative current and the second current source module provides the second positive current in response to a modulated differential off signal to produce the zero current signal and high frequency modulated signal components;

modulation module operably coupled to modulate the differential off signal to produce the modulated differential off signal and to pass the differential charge up signal and the differential charge down signal, wherein errors resulting from nonlinearities between the first and second current source modules are substantially contained in the high frequency modulated signal components;

low pass filter operably coupled to attenuate the high frequency modulated signal components and to pass, substantially unattenuated, the positive current signal, the negative current signal, and the zero current signal to produce a filtered signal;

voltage controlled oscillator operably coupled to produce an output oscillation based on the filtered signal; and

divider module operably coupled to divide the output oscillation by divider value to produce the feedback oscillation, wherein the divider value includes at least an integer portion.

2. The differential linear fractional-N synthesizer of claim 1, wherein the phase and frequency detection module further comprises:

first flip-flop operably coupled to produce a first logic one at a transition edge of the reference oscillation, wherein the first flip-flop is reset to a logic zero based on a reset signal;

second flip-flop operably coupled to produce a second logic one at a transition edge of the feedback oscillation, wherein the second flip-flop is reset to a logic zero based on the reset signal; and

AND gate operably coupled to produce the reset signal based on outputs of the first and second flip-flops, wherein, when the first flip-flop produces the first logic one prior to the second flip-flop producing the second logic one, the phase and frequency detection module is producing the differential charge up signal, when the second flip-flop produces the second logic one prior to the first flip-flop producing the first logic one, the phase and frequency detection module is producing the differential charge down signal, and when the reset signal is asserted, the phase and frequency detection module is producing the differential off signal.

3. The differential linear fractional-N synthesizer of claim 2, wherein the modulation module further comprises:

matching module operably coupled to produce a binary matching signal based on the reset signal; and

logic circuitry operably coupled to produce the modulated differential off signal based on the binary matching signal and the differential off signal and to pass the differential charge up signal and the differential charge down signal.

4. The differential linear fractional-N synthesizer of claim 3, wherein the logic circuitry further comprises:

first exclusive OR gate operably coupled to exclusively OR the outputs of the first and second flip-flops of the phase and frequency detection module;

inverter operably coupled to invert an output of the first exclusive OR gate;

second AND gate operably coupled to logically AND an output of the inverter with the binary matching signal;

second exclusive OR gate operably coupled to exclusively OR the output of the first flip-flop of the phase and frequency detection module with an output of the second AND gate; and

third exclusive OR gate operably coupled to exclusively OR the output of the second flip-flop of the phase and frequency detection module with the output of the second AND gate, wherein outputs of the second and third exclusive OR gates provides the differential charge up signal, the differential charge down signal, and the modulated differential off signal.

5. The differential linear fractional-N synthesizer of claim 3, wherein the matching module further comprises:

dither generator operably coupled to generate a random binary data stream at a frequency great than a corner frequency of the low pass filter; and

zero input delta sigma modulator operably coupled to modulate a zero input in accordance with the random binary data stream to produce the matching binary signal.

6. The differential linear fractional-N synthesizer of claim 1, wherein each of the first and second current source modules further comprises:

current source operably coupled to produce a current; and

switching circuitry response to the differential charge up signal, the differential charge down signal, and the modulated differential off signal to produce the positive, negative, or zero current signal from the current.

7. A linear charge pump comprises:

first current source module operably coupled to provide a first positive current in response to a differential charge up signal and to provide a first negative current in response to a differential charge down signal;

second current source module operably coupled to provide a second positive current in response to the differential charge up signal and a second negative current in response to the differential charge down signal, wherein the first and second positive currents provide a positive current signal, wherein the first and second negative currents provide a negative current signal, and wherein the first current source module provides the first positive current and the second current source module provides the second negative current or the first current source module provides the first negative current and the second current source module provides the second positive current in response to a modulated differential off signal to produce a zero current signal and high frequency modulated signal components; and

modulation module operably coupled to modulate a differential off signal to produce the modulated differential off signal and to pass the differential charge up signal and the differential charge down signal, wherein errors resulting from nonlinearities between the first and second current source modules are substantially contained in the high frequency modulated signal components.

8. The linear charge pump of claim 7, wherein the modulation module further comprises:

matching module operably coupled to produce a binary matching signal based on the reset signal; and

logic circuitry operably coupled to produce the modulated differential off signal based on the binary matching signal and the differential off signal and to pass the differential charge up signal and the differential charge down signal.

9. The linear charge pump of claim 8, wherein the logic circuitry further comprises:

first exclusive OR gate operably coupled to exclusively OR inputs corresponding to the differential charge up signal, the differential charge down signal, and the differential off signal;

inverter operably coupled to invert an output of the first exclusive OR gate;

second AND gate operably coupled to logically AND an output of the inverter with the binary matching signal;

second exclusive OR gate operably coupled to exclusively OR one of the inputs corresponding to the differential charge up signal, the differential charge down signal, and the differential off signal with an output of the second AND gate; and

third exclusive OR gate operably coupled to exclusively OR another one of the inputs corresponding to the differential charge up signal, the differential charge down signal, and the differential off signal with the output of the second AND gate, wherein outputs of the second and third exclusive OR gates provides the differential charge up signal, the differential charge down signal, and the modulated differential off signal.

10. The linear charge pump of claim 8, wherein the matching module further comprises:

dither generator operably coupled to generate a random binary data stream at a frequency great than a corner frequency of the low pass filter; and

zero input delta sigma modulator operably coupled to modulate a zero input in accordance with the random binary data stream to produce the matching binary signal.

11. The linear charge pump of claim 7, wherein each of the first and second current source modules further comprises:

current source operably coupled to produce a current; and

switching circuitry response to the differential charge up signal, the differential charge down signal, and the modulated differential off signal to produce the positive, negative, or zero current signal from the current.

12. A method for generating an output oscillation, the method comprises:

producing a differential charge up signal, a differential charge down signal, or a differential off signal based on at least one of a phase difference between a reference oscillation and a feedback oscillation and a frequency difference between the reference oscillation and the feedback oscillation;

modulating the differential off signal to produce a modulated differential off signal and high frequency modulated signal components;

producing a positive current signal in response to the differential charge up signal;

producing a negative current signal in response to the differential charge down signal;

producing a zero current signal in response to the modulated differential off signal;

filtering the positive current signal, the negative current signal, the zero current signal, and the high frequency modulated signal components such that the high frequency modulated signal components are attenuated and the positive current signal, the negative current signal, and the zero current signal are filtered to produce a filtered signal;

producing the output oscillation based on the filtered signal; and

dividing the output oscillation by divider value to produce the feedback oscillation, wherein the divider value includes at least an integer portion.

13. The method of claim 12, wherein the producing the zero current signal further comprises:

providing a first positive current and a second negative current to produce the zero current signal when the modulated differential off signal is in a first state; and

providing a first negative current and a second positive current to produce the zero current signal when the modulated differential off signal is in a second state.

14. The method of claim 12, wherein the producing the differential charge up signal, the differential charge down signal, or the differential off signal further comprises:

producing a first logic one at a transition edge of the reference oscillation;

resetting the first logic one to a logic zero in accordance with a reset signal;

producing a second logic one at a transition edge of the feedback oscillation;

resetting the second logic one to a logic zero in accordance with the reset signal; and

ANDing the first and second logic ones to produce the reset signal such that, when the first logic one is produced prior to the producing of the second logic one, the differential charge up signal is produced, when the second logic one is produced prior to the producing of the first logic one, the differential charge down signal is produced, and when the reset signal is asserted, the differential off signal is produced.

15. The method of claim 14, wherein the modulating the differential off signal further comprises:

producing a binary matching signal based on the reset signal; and

exclusive ORing the producing and resetting of the first and second logic ones to produce an exclusive OR resultant;

inverting the exclusive OR resultant to produce an inverted exclusive OR resultant;

ANDing the binary matching signal and the inverted exclusive OR resultant to produce an AND resultant;

exclusive ORing the producing and resetting of the first logic one with the AND resultant to produce one leg of the differential charge up signal, one leg of the differential charge down signal or one leg of the modulated differential off signal; and

exclusive ORing the producing and resetting of the second logic one with the AND resultant to produce another leg of the differential charge up signal, another leg of the differential charge down signal or another leg of the modulated differential off signal.

16. The method of claim 15, wherein the producing the binary matching signal further comprises:

generating a random binary data stream at a frequency great than a corner frequency of the filtering; and

delta sigma modulating a zero input in accordance with the random binary data stream to produce the matching binary signal.

17. An apparatus for generating an output oscillation, the apparatus comprises:

processing module; and

memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to;

produce a differential charge up signal, a differential charge down signal, or a differential off signal based on at least one of a phase difference between a reference oscillation and a feedback oscillation and a frequency difference between the reference oscillation and the feedback oscillation;

modulate the differential off signal to produce a modulated differential off signal and high frequency modulated signal components;

produce a positive current signal in response to the differential charge up signal;

produce a negative current signal in response to the differential charge down signal;

produce a zero current signal in response to the modulated differential off signal;

filter the positive current signal, the negative current signal, the zero current signal, and the high frequency modulated signal components such that the high frequency modulated signal components are attenuated and the positive current signal, the negative current signal, and the zero current signal are filtered to produce a filtered signal;

produce the output oscillation based on the filtered signal; and

divide the output oscillation by divider value to produce the feedback oscillation, wherein the divider value includes at least an integer portion.

18. The apparatus of claim 17, wherein the memory further comprises operational instructions that cause the processing module to produce the zero current signal by:

providing a first positive current and a second negative current to produce the zero current signal when the modulated differential off signal is in a first state; and

providing a first negative current and a second positive current to produce the zero current signal when the modulated differential off signal is in a second state.

19. The apparatus of claim 17, wherein the memory further comprises operational instructions that cause the processing module to produce the differential charge up signal, the differential charge down signal, or the differential off signal by:

producing a first logic one at a transition edge of the reference oscillation;

resetting the first logic one to a logic zero in accordance with a reset signal;

producing a second logic one at a transition edge of the feedback oscillation;

resetting the second logic one to a logic zero in accordance with the reset signal; and

ANDing the first and second logic ones to produce the reset signal such that, when the first logic one is produced prior to the producing of the second logic one, the differential charge up signal is produced, when the second logic one is produced prior to the producing of the first logic one, the differential charge down signal is produced, and when the reset signal is asserted, the differential off signal is produced.

20. The apparatus of claim 19, wherein the memory further comprises operational instructions that cause the processing module to modulate the differential off signal by:

producing a binary matching signal based on the reset signal; and

exclusive ORing the producing and resetting of the first and second logic ones to produce an exclusive OR resultant;

inverting the exclusive OR resultant to produce an inverted exclusive OR resultant;

ANDing the binary matching signal and the inverted exclusive OR resultant to produce an AND resultant;

exclusive ORing the producing and resetting of the first logic one with the AND resultant to produce one leg of the differential charge up signal, one leg of the differential charge down signal or one leg of the modulated differential off signal; and

exclusive ORing the producing and resetting of the second logic one with the AND resultant to produce another leg of the differential charge up signal, another leg of the differential charge down signal or another leg of the modulated differential off signal.

21. The apparatus of claim 20, wherein the memory further comprises operational instructions that cause the processing module to produce the binary matching signal by:

generating a random binary data stream at a frequency great than a corner frequency of the filtering; and

delta sigma modulating a zero input in accordance with the random binary data stream to produce the matching binary signal.

22. A radio comprises:

transmitter section operably coupled to receive outbound data and to produce therefrom, in accordance with at least one transmit local oscillation, outbound radio frequency (RF) signals;

receiver section operably coupled to receive inbound RF signals and to produce therefrom, in accordance with at least one receive local oscillation, inbound data; and

local oscillation module operably coupled to produce the at least one transmit local oscillation and the at least one receive oscillation, wherein the local oscillation module includes;

phase and frequency detection module operably coupled to produce a differential charge up signal, a differential charge down signal, or a differential off signal based on at least one of a phase difference between a reference oscillation and a feedback oscillation and a frequency difference between the reference oscillation and the feedback oscillation;

linearized charge pump operably coupled to produce a positive current signal in response to the differential charge up signal, a negative current signal in response to the differential charge down signal, and zero current signal in response to the differential off signal, wherein the linearized charge pump includes;

first current source module operably coupled to provide a first positive current in response to the differential charge up signal and to provide a first negative current in response to the differential charge down signal;

second current source module operably coupled to provide a second positive current in response to the differential charge up signal and to provide a second negative current in response to the differential charge down signal, wherein the first and second positive currents provide the positive current signal, wherein the first and second negative currents provide the negative current signal, and wherein the first current source module provides the first positive current and the second current source module provides the second negative current or the first current source module provides the first negative current and the second current source module provides the second positive current in response to a modulated differential off signal to produce the zero current signal and high frequency modulated signal components;

modulation module operably coupled to modulate the differential off signal to produce the modulated differential off signal and to pass the differential charge up signal and the differential charge down signal, wherein errors resulting from nonlinearities between the first and second current source modules are substantially contained in the high frequency modulated signal components;

low pass filter operably coupled to attenuate the high frequency modulated signal components and to pass, substantially unattenuated, the positive current signal, the negative current signal, and the zero current signal to produce a filtered signal;

voltage controlled oscillator operably coupled to produce an output oscillation based on the filtered signal, wherein the at least one transmit local oscillation and the at least one receive local oscillation are based on the output oscillation; and

divider module operably coupled to divide the output oscillation by divider value to produce the feedback oscillation, wherein the divider value includes at least an integer portion.

23. The radio of claim 22, wherein the phase and frequency detection module further comprises:

first flip-flop operably coupled to produce a first logic one at a transition edge of the reference oscillation, wherein the first flip-flop is reset to a logic zero based on a reset signal;

second flip-flop operably coupled to produce a second logic one at a transition edge of the feedback oscillation, wherein the second flip-flop is reset to a logic zero based on the reset signal; and

AND gate operably coupled to produce the reset signal based on outputs of the first and second flip-flops, wherein, when the first flip-flop produces the first logic one prior to the second flip-flop producing the second logic one, the phase and frequency detection module is producing the differential charge up signal, when the second flip-flop produces the second logic one prior to the first flip-flop producing the first logic one, the phase and frequency detection module is producing the differential charge down signal, and when the reset signal is asserted, the phase and frequency detection module is producing the differential off signal.

24. The radio of claim 23, wherein the modulation module further comprises:

matching module operably coupled to produce a binary matching signal based on the reset signal; and

logic circuitry operably coupled to produce the modulated differential off signal based on the binary matching signal and the differential off signal and to pass the differential charge up signal and the differential charge down signal.

25. The radio of claim 24, wherein the logic circuitry further comprises:

first exclusive OR gate operably coupled to exclusively OR the outputs of the first and second flip-flops of the phase and frequency detection module;

inverter operably coupled to invert an output of the first exclusive OR gate;

second AND gate operably coupled to logically AND an output of the inverter with the binary matching signal;

second exclusive OR gate operably coupled to exclusively OR the output of the first flip-flop of the phase and frequency detection module with an output of the second AND gate; and

third exclusive OR gate operably coupled to exclusively OR the output of the second flip-flop of the phase and frequency detection module with the output of the second AND gate, wherein outputs of the second and third exclusive OR gates provides the differential charge up signal, the differential charge down signal, and the modulated differential off signal.

26. The radio of claim 24, wherein the matching module further comprises:

dither generator operably coupled to generate a random binary data stream at a frequency great than a corner frequency of the low pass filter; and

zero input delta sigma modulator operably coupled to modulate a zero input in accordance with the random binary data stream to produce the matching binary signal.

27. The radio of claim 22, wherein each of the first and second current source modules further comprises:

current source operably coupled to produce a current; and

switching circuitry response to the differential charge up signal, the differential charge down signal, and the modulated differential off signal to produce the positive, negative, or zero current signal from the current.

28. The radio of claim 22, wherein the local oscillation module further comprises:

logic circuitry to produce the at least one transmit local oscillation and the at least one receive local oscillation from the output oscillation.

29. A radio frequency (RF) transmitter comprises:

baseband modulator operably coupled to produce an in-phase (I) component and a quadrature (Q) component from a data stream;

intermediate frequency (IF) module operably coupled to generate an IF signal from the I and Q components based on a feedback local oscillation;

phase and frequency detection module operably coupled to produce a differential charge up signal, a differential charge down signal, or a differential off signal based on at least one of a phase difference between a reference oscillation and the IF signal and a frequency difference between the reference oscillation and the IF signal;

linearized charge pump operably coupled to produce a positive current signal in response to the differential charge up signal, a negative current signal in response to the differential charge down signal, and zero current signal in response to the differential off signal, wherein the linearized charge pump includes;

first current source module operably coupled to provide a first positive current in response to the differential charge up signal and to provide a first negative current in response to the differential charge down signal;

second current source module operably coupled to provide a second positive current in response to the differential charge up signal and to provide a second negative current in response to the differential charge down signal, wherein the first and second positive currents provide the positive current signal, wherein the first and second negative currents provide the negative current signal, and wherein the first current source module provides the first positive current and the second current source module provides the second negative current or the first current source module provides the first negative current and the second current source module provides the second positive current in response to a modulated differential off signal to produce the zero current signal and high frequency modulated signal components;

modulation module operably coupled to modulate the differential off signal to produce the modulated differential off signal and to pass the differential charge up signal and the differential charge down signal, wherein errors resulting from nonlinearities between the first and second current source modules are substantially contained in the high frequency modulated signal components;

low pass filter operably coupled to attenuate the high frequency modulated signal components and to pass, substantially unattenuated, the positive current signal, the negative current signal, and the zero current signal to produce a filtered signal;

voltage controlled oscillator operably coupled to produce an output RF signal based on the filtered signal, wherein the feedback oscillation is based on the output RF signal and a local oscillation.

30. The RF transmitter of claim 29, wherein the phase and frequency detection module further comprises:

first flip-flop operably coupled to produce a first logic one at a transition edge of the reference oscillation, wherein the first flip-flop is reset to a logic zero based on a reset signal;

second flip-flop operably coupled to produce a second logic one at a transition edge of the feedback oscillation, wherein the second flip-flop is reset to a logic zero based on the reset signal; and

AND gate operably coupled to produce the reset signal based on outputs of the first and second flip-flops, wherein, when the first flip-flop produces the first logic one prior to the second flip-flop producing the second logic one, the phase and frequency detection module is producing the differential charge up signal, when the second flip-flop produces the second logic one prior to the first flip-flop producing the first logic one, the phase and frequency detection module is producing the differential charge down signal, and when the reset signal is asserted, the phase and frequency detection module is producing the differential off signal.

31. The RF transmitter of claim 30, wherein the modulation module further comprises:

matching module operably coupled to produce a binary matching signal based on the reset signal; and

logic circuitry operably coupled to produce the modulated differential off signal based on the binary matching signal and the differential off signal and to pass the differential charge up signal and the differential charge down signal.

32. The RF transmitter of claim 31, wherein the logic circuitry further comprises:

first exclusive OR gate operably coupled to exclusively OR the outputs of the first and second flip-flops of the phase and frequency detection module;

inverter operably coupled to invert an output of the first exclusive OR gate;

second AND gate operably coupled to logically AND an output of the inverter with the binary matching signal;

second exclusive OR gate operably coupled to exclusively OR the output of the first flip-flop of the phase and frequency detection module with an output of the second AND gate; and

third exclusive OR gate operably coupled to exclusively OR the output of the second flip-flop of the phase and frequency detection module with the output of the second AND gate, wherein outputs of the second and third exclusive OR gates provides the differential charge up signal, the differential charge down signal, and the modulated differential off signal.

33. The RF transmitter of claim 31, wherein the matching module further comprises:

dither generator operably coupled to generate a random binary data stream at a frequency great than a corner frequency of the low pass filter; and

zero input delta sigma modulator operably coupled to modulate a zero input in accordance with the random binary data stream to produce the matching binary signal.

34. The RF transmitter of claim 29, wherein each of the first and second current source modules further comprises:

current source operably coupled to produce a current; and

switching circuitry response to the differential charge up signal, the differential charge down signal, and the modulated differential off signal to produce the positive, negative, or zero current signal from the current.