Bias filtering module including MOS capacitors

• US 20040102173A1
• Filed: 11/25/2002
• Published: 05/27/2004
• Est. Priority Date: 11/25/2002
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Darabi, Hooman
• Granted Patent: US 6,931,267 B2
• Time in Patent Office: Days
• US Class Current: 455/307
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A bias filtering module with at least two capacitive levels satisfies both a settle time requirement and a filtering requirement using a voltage dependent filter module whose capacitance is a function of a voltage potential on the filtering circuitry output terminal. The final capacitance level is approximately three times larger than the initial capacitance level. MOS capacitors having a voltage dependent charge capacity within the bias filtering module are coupled between a plurality of bias lines and circuit common. In an alternate embodiment, a selectable first group of capacitors are switched into connection within the bias filtering module as a second group of capacitors approximately reach a fully charged state within a specified settle time to provide improved filtering.

Claims

1. A receiver, comprising:

an amplification module for amplifying a received radio frequency (RF) signal to produce an amplified RF signal, wherein the amplification module is biased to a first bias level;

a mixer module coupled to mix the amplified RF signal with a local oscillation to produce a down converted signal having a specified frequency wherein the mixer module is biased to a second bias level;

a bandpass filter module operably coupled to receive and to bandpass filter the down converted signal to produce a filtered signal, wherein the bandpass filter module is biased to a third bias level;

an analog-to-digital (A/D) converter module coupled to receive the filtered signal, the A/D converter module for converting the filtered signal from an analog domain to a digital domain, the A/D converter generating a digital bit stream, wherein the A/D converter module is biased to a fourth bias level;

a processing module coupled to receive and process the digital bit stream, wherein the processing module is biased to a fifth bias level;

logic circuitry coupled to power down at least a portion of one of the amplification module, the mixer module, the bandpass filter module, the A/D converter module, and the processing module during a specified mode of operation and coupled to power up any module powered down during the specified mode of operation whenever the receiver begins to receive the RF signal; and

a bias filtering module coupled to at least one of the amplification module, the mixer module, the bandpass filter module, the A/D converter module and the processing module to provide therefor at least one of the first bias level, second bias level, third bias level, fourth bias level based, and fifth bias level on a voltage dependent filter function, wherein the bias filtering module, for the at least one of the first bias level, the second bias level, the third bias level, the fourth bias level, and the fifth bias level, provides an initial bias level within a specified settle time, relative to a trigger event, for enabling fast power up and further provides a final bias level for improved filtering.

2. The receiver of claim 1 wherein the bias filtering module includes filtering circuitry having a second settlement state value that is a function of a voltage potential on an output terminal of the filtering circuitry.

3. The receiver of claim 1 wherein the bias filtering module includes a plurality of components, each of the plurality of components coupled between a corresponding one of the first, second, third, fourth, and fifth bias levels and circuit common.

4. The receiver of claim 3 wherein each of the plurality of components comprises at least one voltage dependent filter module having an initial capacitance value with an associated initial charge level and a final capacitance value with an associated final charge level and wherein the initial capacitance value is one that is designed to satisfy the specified settle time.

5. The receiver of claim 4 wherein the final capacitance value of the voltage dependent filter module has a charge time that exceeds the specified settle time.

6. The receiver of claim 5 wherein the final capacitance value of the voltage dependent filter module is one that satisfies a specified filtering function.

7. The receiver of claim 6 wherein the specified filtering function is one that bypasses a substantial amount of noise to circuit common.

8. The receiver of claim 4 wherein the voltage dependent filter module is selected by logic circuitry that selects the voltage dependent filter module approximately when the initial charge level is reached within the specified settle time.

9. The receiver of claim 4 wherein the specified settle time is equal to ten micro-seconds and the initial capacitance value that provides the first charge level is equal to ten pico-farads.

10. The receiver of claim 4 wherein the final settle time is greater than 10 micro-seconds and the final capacitance value is equal to 30 pico-farads.

11. The receiver of claim 4 wherein the final capacitance value is at least two times greater than the initial capacitance value.

12. The receiver of claim 4 wherein each of the plurality of components are formed to have at least two charge times wherein a first charge time is less than the specified settle time and wherein a second charge time exceeds the specified settle time.

13. A transmitter, comprising:

a processing module coupled to produce a digital bit stream for transmission wherein the processing module is biased to a first bias level;

a digital-to-analog (D/A) converter module coupled to receive the digital bit stream and to produce an analog baseband frequency signal, wherein the D/A converter module is biased to a second bias level;

an up-conversion module operably coupled to receive the analog baseband frequency signal from the D/A converter module, the up-conversion module for up-converting the analog baseband frequency signal to an RF signal, wherein the up-conversion module is biased to a third bias level;

a radio frequency (RF) output module to receive and amplify the RF signal received from the up-conversion module prior to transmission via a transmitting antenna, wherein the RF output module is biased to a fourth bias level;

logic circuitry coupled to power down at least a portion of one of the processing module, the D/A converter module, the up-conversion module, and the RF output module during a specified mode of operation and coupled to power up any module powered down during the specified mode of operation whenever the transmitter begins to transmit the RF signal; and

a bias filtering module operably coupled to at least one of the processing module, the D/A converter module, the up-conversion module, and the RF output module to provide therefor at least one of the first bias level, the second bias level, the third bias level, and the fourth bias level on a voltage dependent filter module, wherein the bias filtering module, for the at least one of the first bias level, the second bias level, the third bias level, and the fourth bias level, provides an initial bias level within a specified settle time, relative to a trigger event, for enabling fast power up and further provides a final bias level for improved filtering

14. The transmitter of claim 13 wherein the specified settle time is equal to ten microseconds.

15. The transmitter of claim 13, wherein the bias filtering module comprises at least one MOS capacitor coupled between a bias filtering module input terminal and circuit common.

16. The transmitter of claim 15, wherein the at least one MOS capacitor is formed to have an initial capacitance value whose initial charge time is less than or equal to the specified settle time.

17. The transmitter of claim 15, wherein the at least one MOS capacitor is formed to have a final capacitance value whose final charge time is longer than the specified settle time.

18. The transmitter of claim 17, wherein the at least one MOS capacitor final capacitance value requires charging for at least twenty microseconds to obtain at least a ninety percent charge.

19. The transmitter of claim 17 wherein the final charge time is approximately three times the specified settle time.

20. The transmitter of claim 17, wherein the final capacitance value provides a specified filtering function on at least one bias level of the first bias level, the second bias level, the third bias level, and the fourth bias level

21. The transmitter of claim 20, wherein the specified filtering function is one that bypasses a substantial amount of noise to circuit common.

22. The transmitter of claim 21 wherein the voltage dependent filter module is selected by logic circuitry that selects the voltage dependent filter module approximately when the first charge level is reached within the specified settle time.

23. A method for providing power and for filtering a module within a radio transmitter, comprising:

providing power to each of a plurality of modules within the radio transmitter during a first mode of operation;

transitioning to a second mode of operation and powering down at least a portion of at least one of the plurality of modules;

transitioning back to the first mode of operation;

increasing a bias voltage to a first bias voltage level in a bias filtering module coupled between the at least one of the plurality of modules and a circuit common and charging the bias filtering module to a first charge level in a first charge time; and

increasing the bias voltage to a second bias voltage level, wherein the bias filtering module charges to a second charge level to improve filtering for the at least one of the plurality of modules.

24. The method of claim 23 wherein the first mode of operation is a transmission mode in which the transmitter transmits an RF signal.

25. The method of claim 23 wherein the second mode of operation is a non-transmission mode in which the transmitter is not transmitting the RF signal.

26. A method for filtering bias lines within a radio receiver, comprising:

providing power to each of a plurality of modules within a radio receiver during a first mode of operation in which the receiver receives an RF signal

transitioning into a power down mode of operation in which at least a portion of at least one radio receiver module is powered down;

receiving one of a data packet for processing or a power up signal and transitioning into a receive mode of operation;

applying a first voltage level to a bias filtering module;

charging the bias filtering module to reach a first charged condition within a specified settle time;

applying a second voltage level to the bias filtering module; and

charging the bias filtering module to a second charged condition.