Apparatus for testing I/O ports of a computer motherboard
First Claim
1. An apparatus for testing I/O ports of a computer motherboard comprising:
- a circuit board;
a first connector electrically connected to the circuit board, including a plurality of parallel interface data pins, a plurality of parallel interface status pins and a plurality of parallel interface control pins, for establishing electrical connections with corresponding pins of a parallel port of the computer motherboard;
a first test circuit coupled to the first connector, comprising a logic device coupled to logically operate the parallel interface data pins and the parallel interface control pins on the first connector and to provide a set of logic signals to a portion of the parallel interface status pins on the first connector;
a second connector electrically connected to the circuit board, including a pair of universal serial bus (USB) interface differential data pins, for establishing electrical connections with corresponding pins of a USB port of the computer motherboard; and
a second test circuit coupled to the second connector, comprising;
a first resistor connected between a first voltage source and one of the USB interface differential data pins;
a second resistor connected between a second voltage source and the other USB interface differential data pin; and
a third resistor connected between the pair of USB interface differential data pins;
wherein the first, the second and the third resistors are connected in series.
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Accused Products
Abstract
An apparatus for testing I/O ports of a computer motherboard. A non-volatile memory on a computer motherboard under test stores a test code instead of a normal BIOS code to initialize the computer motherboard under test and test its I/O ports. The computer motherboard under test is booted from the test code. For the I/O ports to be tested, a CPU on the computer motherboard under test executes test routines in the test code. The apparatus of the invention is connected to the computer motherboard under test so as to cooperate with the test routines in testing the I/O ports. Furthermore, the inventive apparatus includes connectors and test circuits for establishing electrical connections with corresponding pins of the I/O ports to be tested and checking each pin with the test routines.
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Citations
46 Claims
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1. An apparatus for testing I/O ports of a computer motherboard comprising:
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a circuit board;
a first connector electrically connected to the circuit board, including a plurality of parallel interface data pins, a plurality of parallel interface status pins and a plurality of parallel interface control pins, for establishing electrical connections with corresponding pins of a parallel port of the computer motherboard;
a first test circuit coupled to the first connector, comprising a logic device coupled to logically operate the parallel interface data pins and the parallel interface control pins on the first connector and to provide a set of logic signals to a portion of the parallel interface status pins on the first connector;
a second connector electrically connected to the circuit board, including a pair of universal serial bus (USB) interface differential data pins, for establishing electrical connections with corresponding pins of a USB port of the computer motherboard; and
a second test circuit coupled to the second connector, comprising;
a first resistor connected between a first voltage source and one of the USB interface differential data pins;
a second resistor connected between a second voltage source and the other USB interface differential data pin; and
a third resistor connected between the pair of USB interface differential data pins;
wherein the first, the second and the third resistors are connected in series. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An apparatus for testing I/O ports of a computer motherboard comprising:
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a computer motherboard under test comprising;
a plurality of I/O ports including a parallel port and a USB port;
a non-volatile memory for storing a test code, instead of a basic input-output system (BIOS) code, to initialize the computer motherboard under test and test the I/O ports; and
a central processing unit (CPU) booting from the test code in the non-volatile memory for executing the test code to test the I/O ports of the computer motherboard under test;
a first connector, including a plurality of parallel interface data pins, a plurality of parallel interface status pins and a plurality of parallel interface control pins, for establishing electrical connections with corresponding pins of the parallel port of the computer motherboard under test;
a first test circuit, coupled to the first connector, comprising a logic device coupled to logically operate the parallel interface data pins and the parallel interface control pins on the first connector and to provide a set of logic signals to a portion of the parallel interface status pins on the first connector;
a second connector, including a pair of universal serial bus (USB) interface differential data pins, for establishing electrical connections with corresponding pins of the USB port of the computer motherboard under test; and
a second test circuit, coupled to the second connector, comprising;
a first resistor connected between a first voltage source and one of the USB interface differential data pins;
a second resistor connected between a second voltage source and the other USB interface differential data pin; and
a third resistor connected between the pair of USB interface differential data pins;
wherein the first, the second and the third resistors are connected in series. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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Specification