Appliance, including a flash memory, that is robust under power failure

• US 20040103238A1
• Filed: 11/26/2002
• Published: 05/27/2004
• Est. Priority Date: 11/26/2002
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Lasser, Menahem, Avraham, Meir
• Granted Patent: US 7,003,620 B2
• Time in Patent Office: Days
• US Class Current: 711/102
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

An appliance that includes a host device and a memory unit with a primary memory, and a method of operating the appliance. According to one aspect of the appliance, the primary memory is nonvolatile and the memory unit also includes a volatile memory a power sensor and a controller. When the power sensor detects interruption of power to the memory unit, the controller copies data selectively from the volatile memory to the primary memory. Power for this copying is provided by a secondary power source such as a battery or a capacitor. According to another aspect of the appliance, the appliance includes primary and secondary power sources, and the memory unit also includes a charge pump whose functions include both boosting power from the primary source for the primary memory and charging the secondary source.

Claims

1. A method of operating an appliance that includes a host device and a memory unit, the memory unit including a nonvolatile memory, the method comprising the steps of:

(a) providing a volatile memory for storing data; and

(b) upon interruption of power to the memory unit, selectively writing said data then stored in said volatile memory to the nonvolatile memory.

2. The method of claim 1, wherein said volatile memory is a cache memory for caching said data prior to writing said data to the nonvolatile memory, and wherein said selective writing is writing at least a portion of said data of only one data class then cached in said cache memory, said one data class being selected from the group consisting of system data and user data.

3. The method of claim 2, wherein said one data class is user data.

4. The method of claim 2, wherein said one data class is system data.

5. The method of claim 4, wherein said at least portion of said system data includes file allocation data.

6. The method of claim 4, wherein said at least portion of said system data includes a copy of a memory buffer that is used by the host device to accumulate user data.

7. The method of claim 4, wherein said at least portion of said system data includes a description of a status of the host device.

8. The method of claim 4, wherein said at least portion of said system data includes an identification of an interrupted operation.

9. The method of claim 1, wherein said volatile memory is a cache memory for caching said data prior to writing said data to the nonvolatile memory,. and wherein said selective writing is writing only a portion of said data then cached in said cache memory to the nonvolatile memory.

10. The method of claim 9, wherein said portion of said data includes only user data.

11. The method of claim 9, wherein said portion of said data includes only system data.

12. The method of claim 11, wherein said system data include file allocation data.

13. The method of claim 11, wherein said system data include a copy of a memory buffer that is used by the host device to accumulate user data.

14. The method of claim 11, wherein said system data include a description of a status of the host device.

15. The method of claim 11, wherein said system data include an identification of an interrupted operation.

16. The method of claim 1, wherein said volatile memory is for storing system data, wherein said selective writing is effected only upon said interruption of power to the memory unit, and wherein said selective writing is writing at least a portion of said system data then stored in said volatile memory to the nonvolatile memory.

18. The method of claim 16, wherein said at least portion of said system data includes file allocation data.

19. The method of claim 16, wherein said at least portion of said system data includes a copy of a memory buffer that is used by the host device to accumulate user data.

20. The method of claim 16, wherein said at least portion of said system data includes a description of a status of the host device.

21. The method of claim 16, wherein said at least portion of said system data includes an identification of an interrupted operation.

22. The method of claim 1, wherein said interruption of power is an interruption of power from a primary power source in the host device, the method further comprising the step of:

(c) providing power from a secondary power source for powering said selective writing of said data to the nonvolatile memory.

23. The method of claim 22, wherein said secondary power source includes a battery.

24. The method of claim 22, wherein said secondary power source includes a capacitor.

25. The method of claim 22, further comprising the step of:

(d) upon resumption of power from said primary power source to the memory unit, writing said selectively written data from the nonvolatile memory to said volatile memory.

26. The method of claim 1, further comprising the step of:

(c) upon resumption of power to the memory unit, writing said selectively written data from the nonvolatile memory to said volatile memory.

27. The method of claim 1, further comprising the step of:

(c) reserving a portion of the nonvolatile memory to which said data is selectively written upon said interruption of power to the memory unit,

said portion of the nonvolatile memory being exclusively for said selective writing of said data upon said interruption of power.

17. The method of claim i 16, wherein said volatile memory is for storing only said system data.

28. An appliance comprising:

(a) a memory unit including;

(i) a nonvolatile memory;

(ii) a volatile memory for storing data;

(iii) a power sensor for receiving and detecting power supplied by a primary power source external to said memory unit, said power being for powering said memory unit, and

(iv) a controller for, upon receiving an indication from said power sensor of an interruption of said power, selectively writing said data then stored in said volatile memory to said nonvolatile memory.

29. The appliance of claim 28, wherein said volatile memory is a cache memory for caching said data prior to writing said data to said nonvolatile memory, and wherein said selective writing is writing at least a portion of said data of only one data class then cached in said cache memory, said one data class being selected from the group consisting of system data and user data.

30. The appliance of claim 28, wherein said volatile memory is a cache memory for caching said data prior to writing said data to said nonvolatile memory, and wherein said selective writing is writing only a portion of said data then cached in said cache memory to said nonvolatile memory.

31. The appliance of claim 28, wherein said volatile memory is for storing system data, wherein said selective writing is effected only upon said interruption of said power, and wherein said selective writing is writing at least a portion of said system data then stored in said volatile memory to said nonvolatile memory.

32. The appliance of claim 31, wherein said volatile memory is for storing only said system data.

33. The appliance of claim 28, further comprising:

(b) a host device including said primary power source.

34. The appliance of claim 28, further comprising:

(b) a secondary power source for providing power for said writing, by said controller, of said at least portion of said data to said nonvolatile memory.

35. The appliance of claim 34, wherein said secondary power source includes a battery.

36. The appliance of claim 34, wherein said secondary power source includes a capacitor.

37. The appliance of claim 34, wherein said secondary power source is included in said memory unit.

38. The appliance of claim 34, further comprising:

(c) a host device including;

(i) said primary power source and

(ii) said secondary power source.

39. The appliance of claim 28, wherein said volatile cache memory and said controller are fabricated on a common substrate.

40. The appliance of claim 28, wherein said nonvolatile memory and said volatile cache memory are fabricated on a common substrate.

41. The appliance of claim 28, wherein said nonvolatile memory includes a portion thereof that is reserved exclusively for said writing, by said controller, of said at least portion of said data.

42. An appliance comprising:

(a) a primary power source;

(b) a secondary power source; and

(c) a memory unit that receives power from said primary power source at a first voltage and that includes;

(i) a primary memory, and

(ii) a charge pump for;

(A) boosting said power from said primary power source to a second voltage for said primary memory, and

(B) charging said secondary power source.

43. The appliance of claim 42, wherein said secondary power source includes a batten,.

44. The appliance of claim 42, wherein said secondary power source includes a capacitor.

45. The appliance of claim 42, wherein said secondary power source is included in said memory unit.

46. The appliance of claim 42, further comprising:

(d) a host device that includes both said primary power source and said secondary power source.

47. The appliance of claim 42, wherein said secondary power source is operative to provide said secondary power to said primary memory at said second voltage.

48. The appliance of claim 42, wherein said primary memory is nonvolatile, and wherein said memory unit further includes:

(iii) a volatile cache memory for caching data prior to writing said data to said primary memory;

(iv) a power sensor for receiving and detecting said power from said primary power source; and

(v) a controller that, upon receiving an indication from said power sensor of an interruption of said power from said primary power source, uses power from said secondary power source to write at least a portion of said data then cached in said volatile cache memory to said primary memory.

49. The appliance of claim 48, wherein said volatile cache memory and said controller are fabricated on a common substrate.

50. The appliance of claim 48, wherein said primary memory and said volatile cache memory are fabricated on a common substrate.

51. The appliance of claim 42, wherein said primary memory is nonvolatile, and wherein said memory unit further includes:

(iii) a volatile cache memory for caching data prior to writing said data to said primary memory;

(iv) a power sensor for receiving and detecting said power from said primary power source; and

(v) a controller that, upon receiving an indication from said power sensor of an interruption of said power from said primary power source, uses power from said secondary power source to write only a portion of said data then cached in said volatile cache memory to said primary memory.

52. The appliance of claim 51, wherein said volatile cache memory and said controller are fabricated on a common substrate.

53. The appliance of claim 51, wherein said primary memory and said volatile cache memory are fabricated on a common substrate.

54. The appliance of claim 42, wherein said primary memory is nonvolatile, and wherein said memory unit further includes:

(iii) a volatile memory for storing system data;

(iv) a power sensor for receiving and detecting said power from said primary power source; and

(v) a controller that, upon receiving an indication from said power sensor of an interruption of said power from said primary power source, uses power from said secondary power source to write at least a portion of said system data then stored in said volatile memory to said primary memory.

55. The appliance of claim 54, wherein said volatile memory and said controller are fabricated on a common substrate.

56. The appliance of claim 54, wherein said primary memory and said volatile memory are fabricated on a common substrate.

57. A memory device comprising:

(a) a nonvolatile memory, a portion whereof is reserved exclusively for copying thereto at least a portion of data stored in the memory device upon interruption of power from a power source external to the memory device.

58. The memory device of claim 57, further comprising:

(b) a volatile memory wherein said at least portion of said data is stored.