Adjusting voltage supplied to a processor in response to clock frequency

• US 20040103330A1
• Filed: 11/25/2002
• Published: 05/27/2004
• Est. Priority Date: 11/25/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bonnett, William B.
• Granted Patent: US 6,996,730 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for adjusting the clock frequency and voltage supplied to an integrated circuit is provided. A request signal is sent to the clock, and in response, the clock lowers the clock frequency supplied to the integrated circuit. A frequency detection circuit monitors the clock signal and causes a voltage regulator to reduce the voltage supplied to the integrated circuit in response to the reduced clock frequency. Similarly, a request signal is sent to the clock, and in response, the clock raises the clock frequency supplied to the integrated circuit. The frequency detection circuit monitors the clock signal and causes a voltage regulator to raise the voltage supplied to the integrated circuit in response to the increased clock frequency. The slew rate of the clock is controlled so that at least a minimum required voltage for each operating frequency is provided while the clock frequency is being changed. In this manner, reliable operation of the processor is assured while the clock speed and operating voltage are being changed.

Claims

1. A method of adjusting power consumption of a computer processor, the method comprising the steps of:

sending a first signal from a computer subsystem comprising the computer processor to a clock circuit in response to a first predetermined condition, the clock circuit providing a clock signal having a frequency to the computer processor;

decreasing the frequency of the clock signal from a high frequency to a lower frequency in response to the first signal from the computer subsystem;

detecting a decrease in the frequency of the clock signal and communicating said decrease to a voltage regulator in response to the step of decreasing the clock frequency, the voltage regulator having an output voltage that is provided to the computer processor; and

decreasing the output voltage of the voltage regulator from a high voltage to a lower voltage in response to the step of detecting.

2. The method of claim 1, further comprising the steps of:

sending a second signal from the computer subsystem to the clock circuit in response to a second predetermined condition;

increasing the frequency of the clock signal from a low frequency to a higher frequency in response to the second signal;

detecting an increase in the frequency of the clock signal and communicating said increase to the voltage regulator in response to the step of increasing the clock frequency; and

increasing the output voltage of the voltage regulator from the low voltage to a higher voltage in response to the step of detecting an increase in the frequency of the clock signal.

3. The method of claim 2, wherein the step of increasing the frequency of the clock signal comprises limiting a slew rate of the clock circuit so that at least a minimum required voltage for each operating frequency is provided while the frequency of the clock signal is being increased.

4. The method of claim 1, wherein the processor, the computer subsystem, the clock, and the voltage regulator are part of a battery-operated computer system, and the first predetermined condition is a low battery power condition detected by the computer subsystem.

5. The method of claim 1, wherein the first predetermined condition is a request for low power mode operation detected by the computer subsystem.

6. The method of claim 1, wherein the first predetermined condition is an overtemp condition detected by the computer subsystem.

7. The method of claim 2, wherein the second predetermined condition is a request for normal operation mode detected by the computer subsystem.

8. The method of claim 2, wherein the second predetermined condition is detected by the computer subsystem after an overtemp condition ends.

9. A method of adjusting power consumption of a computer processor, the method comprising the steps of:

sending a first signal from a computer subsystem comprising the computer processor to a clock circuit in response to a first predetermined condition, the clock circuit providing a clock signal having a frequency to the computer processor;

increasing the frequency of the clock signal from a low frequency to a higher frequency in response to the first signal from the computer subsystem;

detecting an increase in the frequency of the clock signal and communicating said increase to a voltage regulator in response to the step of increasing the clock frequency, the voltage regulator having an output voltage that is provided to the computer processor; and

increasing the output voltage of the voltage regulator from a low voltage to a higher voltage in response to the step of detecting.

10. The method of claim 9, wherein the step of increasing the frequency of the clock signal comprises limiting a slew rate of the clock circuit so that at least a minimum required voltage for each operating frequency is provided while the frequency of the clock signal is being increased.

11. The method of Clam 10, further comprising the step of determining the minimum required voltage for each operating frequency.

12. A computer system comprising:

a computer subsystem including a processor;

a clock circuit having a clock input coupled to the computer subsystem, a clock signal output coupled to the processor for supplying a clock frequency to the processor, the clock circuit operable to transition to a different clock frequency in response to a request signal from the computer subsystem;

a frequency detector connected to the clock signal having an output for indicating a change in frequency of the clock signal; and

a voltage regulator coupled to the frequency detector and having a regulator output coupled to and supplying a voltage to the processor, the regulator operable to transition the output to a different voltage when the frequency detector output indicates a change in clock signal frequency is occurring.

13. The computer system of claim 12, wherein the clock circuit has a limited slew rate, such that at least a minimum required voltage for each operating frequency is provided while the frequency of the clock signal is being changed.

14. The computer system of claim 13, wherein the clock circuit has a first slew rate while the frequency is being increased and a different slew rate while the frequency is being decreased.

15. The computer system of claim 12, wherein the computer system is battery-operated.

16. The computer system of claim 15, wherein the request signal is sent from a battery charge monitor in the computer subsystem to the clock input.

17. The computer system of claim 12, wherein the request signal is sent from a performance monitor in the computer subsystem to the clock input.

18. The computer system of claim 12, wherein the request signal is sent to the clock input from a temperature detector in the computer subsystem.

19. The digital system according to claim 12 being a wireless device, further comprising:

an integrated keyboard connected to the processor via a keyboard adapter;

a display, connected to the processor via a display adapter;

radio frequency (RF) circuitry connected to the processor; and

an aerial connected to the RF circuitry.