Method and circuits for localizing defective interconnect resources in programmable logic devices

• US 20040103354A1
• Filed: 11/07/2003
• Published: 05/27/2004
• Est. Priority Date: 10/25/2002
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Mark, David, Fan, Yuezhen, Ling, Zhi-Min, Li, Xiao-Yu
• Granted Patent: US 7,145,344 B2
• Time in Patent Office: Days
• US Class Current: 714/725
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.

Claims

1. A method of monitoring a manufacturing process for a plurality of programmable logic devices (PLDS) of a PLD type, each of the PLDs including a first collection of interconnect resources occupying a first conductive layer and a second collection of interconnect resources occupying a second conductive layer, the method comprising:

a. for each of the PLDS;

i. instantiating a number of test circuits on the PLD, the test circuits including test-circuit interconnect resources selected from the first and second collections of interconnect resources;

ii. activating the test circuits to pass signals through the test-circuit interconnect resources;

iii. monitoring the activated test circuits to identify failed test circuits; and

iv. for each of the failed test circuits, storing data representative of the test-circuit interconnect resources of the failed test circuit, the data differentiating the test-circuit interconnect resources selected from the first collection of interconnect resources from the test-circuit interconnect resources selected from the second collection of interconnect resources; and

b. calculating the probability of failures in the first conductive layer using the stored data of a plurality of the failed test circuits identified during the monitoring of the activated test circuits.

2. The method of claim 1, wherein the first collection of interconnect resources includes a first plurality of interconnect lines, wherein the second collection of interconnect resources includes a second plurality of interconnect lines, each of the second plurality of interconnect lines being at least twice as long as each of the first plurality of interconnect lines, and wherein at least one of the test circuits includes more than twice as many of the second plurality of interconnect lines as the first plurality of interconnect lines.

3. The method of claim 1, wherein each PLD includes an array of logic blocks, and wherein each of the second plurality of interconnect lines extends along six of the logic blocks.

4. The method of claim 1, wherein calculating the probability of failures in the first conductive layer comprises comparing, from the data stored in connection with the failed test circuits, a first number of the test-circuit interconnect resources selected from the first collection of interconnect resources with a second number of the test-circuit interconnect resources selected from the second collection of interconnect resources.

5. The method of claim 1, further comprising calculating the probability of failures in the second conductive layer using the stored data of the plurality of the failed test circuits identified during the monitoring of the activated test circuits.

6. The method of claim 1, further comprising modifying the manufacturing process in response to the calculated probability.

7. A programmable logic device (PLD) comprising:

a. an array of configurable logic blocks;

b. a first collection of interconnect lines occupying a conductive layer and having a first length;

c. a second collection of interconnect lines having a second length less than the first length;

d. programmable interconnect points selectively interconnecting ones of the first collection of interconnect lines, ones of the second collection of interconnect lines, and ones of the first collection of interconnect lines to ones of the second collection of interconnect lines; and

e. a test circuit instantiated in the PLD using a subset of the configurable logic blocks, at least one of the second collection of interconnect lines, at least three of the first collection of interconnect lines for each of the second collection of interconnect lines used, and a subset of the programmable interconnect points.

8. The PLD of claim 7, wherein the configurable logic blocks extend in rows and columns, and wherein six consecutive configurable logic blocks in one of the columns extends a distance of about the first length.

9. The PLD of claim 7, further comprising a plurality of output pins programmably connected to ones of the programmable interconnect points disposed between ones of the first collection of interconnect lines.

10. The PLD of claim 7, wherein at least three interconnected ones of the first collection of interconnect lines extend in series between a first and a second of the configurable logic blocks.

11. The PLD of claim 10, wherein the at least three interconnected ones of the first collection of interconnect lines define a signal path between the first and second configurable logic blocks, the PLD further comprising first and second output pins connected to the signal path.

12. The PLD of claim 11, wherein the first output pin connects between a first and a second of the at least three interconnected ones of the first collection of interconnect lines and wherein the second output pin connects between the second and a third of the at least three interconnected ones of the first collection of interconnect lines.

13. The PLD of claim 7, wherein at least one of the subset of the configurable logic blocks used in the test circuit is configured as a register.

14. A test method for a programmable logic device, the programmable logic device including an array of configurable logic blocks, a first collection of interconnect lines each extending a first length in a conductive layer, and a second collection of interconnect lines each extending a second length less than half the first length, the method comprising:

a. programmably connecting a first of the configurable logic blocks to a second of the configurable logic blocks via a signal path, the signal path including a first number of the first collection of interconnect lines and a second number of the second collection of interconnect lines, wherein the first number is at least twice the second number;

b. conveying a signal from the first of the configurable logic blocks to the second of the configurable logic blocks via the signal path; and

c. monitoring the signal at a plurality of points along the signal path.

15. The test method of claim 14, further comprising, before conveying the signal, setting the signal path to a first voltage representative of a first logic level and presetting the first configurable logic block to a second voltage representative of a second logic level.

16. The test method of claim 15, further comprising, before conveying the signal, presetting the second configurable logic block to the first voltage.

17. The test method of claim 15, further comprising, before conveying the signal, presetting the second configurable logic block to the second voltage.

18. The test method of claim 14, wherein some of the second collection of interconnect lines extend in a second conductive layer and others of the second collection of interconnect lines extend in a third conductive layer.

19. The test method of claim 14, wherein the programmable logic device includes a row of configurable logic blocks, and wherein six consecutive configurable logic blocks in the row extend a distance of about the first length.