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Method and circuits for localizing defective interconnect resources in programmable logic devices

  • US 20040103354A1
  • Filed: 11/07/2003
  • Published: 05/27/2004
  • Est. Priority Date: 10/25/2002
  • Status: Active Grant
First Claim
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1. A method of monitoring a manufacturing process for a plurality of programmable logic devices (PLDS) of a PLD type, each of the PLDs including a first collection of interconnect resources occupying a first conductive layer and a second collection of interconnect resources occupying a second conductive layer, the method comprising:

  • a. for each of the PLDS;

    i. instantiating a number of test circuits on the PLD, the test circuits including test-circuit interconnect resources selected from the first and second collections of interconnect resources;

    ii. activating the test circuits to pass signals through the test-circuit interconnect resources;

    iii. monitoring the activated test circuits to identify failed test circuits; and

    iv. for each of the failed test circuits, storing data representative of the test-circuit interconnect resources of the failed test circuit, the data differentiating the test-circuit interconnect resources selected from the first collection of interconnect resources from the test-circuit interconnect resources selected from the second collection of interconnect resources; and

    b. calculating the probability of failures in the first conductive layer using the stored data of a plurality of the failed test circuits identified during the monitoring of the activated test circuits.

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