Semiconductor quantum cryptographic device and method

• US 20040104410A1
• Filed: 08/04/2003
• Published: 06/03/2004
• Est. Priority Date: 08/02/2002
• Status: Abandoned Application

• Current Assignee: Arizona Board of Regents (University of Arizona)
• Original Assignee: Arizona Board of Regents (University of Arizona)
• Inventors: Gilbert, Matthew J., Ferry, David K.
• Application Number:
  US10/634,520
• Publication Number:
  US 20040104410A1
• Time in Patent Office: Days
• US Class Current: 257/202
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: H04L 9/0858 Details about key distillation or coding, e.g. reconciliation, error correction, privacy amplification, polarisation coding or phase coding

Abstract

One of two input bias states to a qubit semiconductor waveguide gate controls the transmission of charge carriers to the output of one of two parallel waveguides. Intermediate the ends of the waveguides is a coupling. It permits charge carriers introduced at the input of one of the waveguides to either pass directly along that waveguide to an output end thereof or to move to the other waveguide to be received at that waveguide'"'"'s output end as determined by an electrical or magnetic bias applied to the device. Acting thus, the gate can be used as a gate in quantum computation. For purposes of encryption, spin polarization of the carriers is controlled. The carriers (electrons, for example) can be in polarized to a single up or down spin condition at a quantum point contact by application of a magnetic field or they can be left unpolarized. The alternative appearance of the carriers at the first or second waveguide output and the spin polarization or lack thereof afford two binary nonorthogonal characteristics of a digital communication under the control of the sender. This permits known cryptographic techniques to be applied to develop an encryption key and encrypt communications between sender and receiver. Attempted decryption by any unauthorized person will be apparent. In an exemplary embodiment the first waveguide is of a uniform width, 35 nm, the second waveguide increases in width, from 25 nm at the input side of the gate to 45 nm at the output side of the coupling. The coupling, a tunneling region, is 335 nm in length.

Claims

1. A quantum gate comprising two waveguides, an input section of at least one of the waveguides leading to a coupling region where the two waveguides are coupled, an output section of each of the waveguides leading from the coupling region to an output end of the waveguide, and at least one bias element operative to apply one of an electrical and magnetic bias to the gate to cause carriers moving through the input section of the at least one waveguide into the coupling region to be coupled to one or the other of the output sections of the waveguides in dependence on application of the bias.

2. The quantum gate of claim 1, wherein the coupling region is a tunneling region for passing carriers from the at least one waveguide to the other waveguide by tunneling.

3. The quantum gate of either claim 1 or 2, wherein the at least one bias element is operative to apply an electrical bias across the gate to force carrier movement across the coupling region from the input section of the at least one waveguide to one or the other of the output sections.

4. The quantum gate of either claim 1 or 2, wherein the at least one bias element is operative to apply a magnetic bias to the gate to force carrier movement across the coupling region from the input of the at least one waveguide to one or the other of the output sections.

5. The quantum gate of claim 4, wherein the bias element is a conductor proximate the coupling region.

6. The quantum gate of either claim 1 or 2, wherein the waveguides and the coupling region are a part of a semiconductor structure.

7. The quantum gate of claim 6, the semiconductor structure being of a InAs/InGaAs heterostructure.

8. The quantum gate of either claim 1 or 2, wherein the at least one waveguide is of substantially uniform width and the other waveguide has an output region that is wider than the width of the at least one waveguide.

9. The quantum gate of claim 8, wherein the other waveguide has an input region leading to the coupling region that is narrower than the output region of that waveguide.

10. The quantum gate of either claim 1 or 2, wherein the coupling region is 300 to 450 nm in length.

11. The quantum gate of claim 10, wherein the waveguides are 20 to 50 nm in width.

12. The quantum gate of either claim 1 or 2, wherein the waveguides are separated by a potential barrier at locations other than the coupling region.

13. The quantum gate of claim 9, wherein the input and output regions of the waveguides are separated by a potential barrier.

14. The quantum gate of claim 12, wherein the potential barriers comprise deposited conductors.

15. The quantum gate of claim 12, further comprising potential barriers defining edges of the waveguides spaced from the potential barriers separating the waveguides.

16. The quantum gate of claim 15, wherein the potential barriers comprise deposited conductors.

19. The quantum gate of either claim 1 or 2, further comprising means associated with the input region of the at least one waveguide operative to modify a quantum characteristic of charge carriers moving in that input region towards the coupling region.

20. The quantum gate of claim 19, wherein the quantum characteristic is electron spin, whereby carriers moving in the input region of the at least waveguide are selectively electron spin polarized by operation of the means to modify a quantum characteristic.

21. The quantum gate of claim 19, wherein the quantum characteristic is electron spin and wherein the means to modify a quantum characteristic is a quantum point contact (QPC) and a source of magnetic field associated with the input region of the at least one waveguide.

22. The quantum gate of either claim 1 or 2, further comprising a quantum point contact and a source of magnetic field associated with the input region of the at least one waveguide operative selectively to effect electron spin polarization of carriers moving in that input region.

23. The quantum gate of either claim 1 or 2, wherein the charge carriers are electrons.

24. The quantum gate of either claim 1 or 2, wherein the waveguides are defined by deposited metal conductors operative to develop potential barriers in a semiconductor substrate on which they are deposited and in which the charge carriers move.

17. The quantum gate of 13, further comprising potential barriers defining edges of the waveguides spaced from the potential barriers separating the waveguides.

18. The quantum gate of claim 17, wherein the potential barriers comprise deposited conductors.

25. A semiconductor gate device comprising:

(a) a first means for communicating a number of charge carriers from a first location to a second location,

(b) a second means for communicating a number of charge carriers to the second location,

(c) means located intermediate first and second ends of the first means for communicating for coupling the first means for communicating to the second means for communicating, and

(d) means for applying at least one of a magnetic and an electrical bias to charge carriers moving in the first means for communicating to determine to which of the first and the second means for communicating the charge carriers move via the coupling means.

26. The gate device of claim 25, wherein the first location is a first end of the device where the charge carriers are introduced into the first means for communicating, and the second location is a second end of the device to which the charge carriers move.

27. The gate device of claim 26, wherein the first and second communicating means are first and second waveguides, respectively.

28. The gate device of claim 27, wherein the means for coupling is a tunneling region.

29. The gate device of claim 28, wherein the means for applying at least one of a magnetic and an electrical bias comprises means for applying a magnetic bias across the device to influence which of the first and second waveguides delivers the charge carriers to the second end of the device.

30. The gate device of claim 28, wherein the means for applying at least one of a magnetic and an electrical bias comprises a means for applying an electrical bias across the device to influence which of the first and second waveguides delivers the charge carriers to the second end of the device.

31. The gate device of claim 25, further comprising means for influencing a quantum state of the charge carriers.

32. The gate device of claim 31, wherein the means for influencing a quantum state of the charge carriers comprises means for effecting electron spin polarization.

33. The gate device of claim 32, wherein the means for effecting spin polarization comprises a quantum point contact and means for applying an magnetic field at the quantum point contact.

34. The gate device of claim 33, wherein the quantum point contact is imbedded in the first means for communicating at a location between the first location and the means for coupling.

35. A semiconductor waveguide gate device comprising:

(a) a first waveguide boundary,

(b) a second waveguide boundary spaced from and substantially parallel to the first waveguide boundary,

(c) a first metallic member defining a first waveguide separating boundary protruding between the first waveguide boundary and the second waveguide boundary,

(d) a second metallic member defining a second waveguide separating boundary protruding towards the first electrode between the first waveguide boundary and the second waveguide boundary,

(e) each of the first and second metallic members having edges facing the first waveguide boundary to define a potential barrier spaced substantially the same distance a from the first waveguide boundary,

(f) each of the first and second metallic members having a further edge facing the second waveguide boundary,

(i) the further edge of the first metallic member being spaced from the second waveguide boundary to produce a potential barrier a distance b from the second waveguide boundary,

(ii) the further edge of the second metallic member being spaced from the second waveguide to produce a potential barrier a distance c from the second waveguide boundary that is greater than a,

(iii) the further potential barriers of the first and second metallic members forming with the second waveguide boundary a second waveguide along the second waveguide boundary,

(g) the first and second metallic members having ends separated by a coupling, and

(h) bias applying means located to selectively apply one of a magnetic and an electrical bias to charged particles moving in the first and second waveguides.

36. A semiconductor quantum cryptography system comprising two parallel waveguides, separated by an electrostatic potential barrier and coupled via a tunnel region, a top one of the two waveguides having a uniform width of substantially 35 nm with a small quantum point contact (QPC) with a width of about 35 nm and a length of about 20 nm embedded in an input side of an input waveguide, a further one of the two waveguides being narrowed at its source end to substantially 25 nm and widened to a width of substantially 45 nm on an output side of the tunnel region, and means for controlling spin of the electron, either up or down depending on the sign of an applied filtering magnetic field, and to form with the location of the electron density two non-orthogonal bases for encryption of bits.

37. The semiconductor quantum cryptography system according to claim 36, wherein the electrostatic potential barrier that separates the input and output waveguides begins with a width of substantially 50 nm and then narrows to substantially 25 nm on the output side of the tunnel region.

38. The semiconductor quantum cryptography system according to claim 37, further comprising doping to set a Fermi level that corresponds to a Fermi energy where one mode propagates in the input waveguide.

39. A method of transistor quantum gate operation comprising:

(a) providing in a semiconductor substrate a first waveguide,

(b) providing in the semiconductor substrate a second waveguide,

(c) providing a coupling between the first and the second waveguide,

(d) moving a charge carrier current in one of the waveguides, and

(e) selectively controlling the path of electron current to one or the other of outputs of the waveguides by applying at least one of an electrical and a magnetic bias to the electron current to cause tunneling of the current in the coupling.

40. The method of transistor quantum gate operation according to claim 39, wherein steps (a) and (b) comprise developing barrier potentials in the substrate to define the waveguides.

41. The method of transistor quantum gate operation according to claim 40, wherein developing the barrier potentials comprises:

(i) developing a first barrier potential separating the waveguides at their input ends between inputs to the waveguides and the coupling, and

(ii) developing a second barrier potential separating the waveguides at their output ends between outputs from the waveguides and the coupling.

42. The method of transistor quantum gate operation according to claim 41, wherein developing the first and second barrier potentials comprises defining one waveguide that is wider at its output end than width of the other waveguide at its input end.

43. The method of transistor quantum gate operation according to claim 39, further comprising selectively polarizing the electron spin of charge carriers moved in one of the waveguides.

44. A method of encryption between a sender and a receiver in a solid state device comprising the sender randomly choosing numbers a and b where a corresponds to a location of an electron density, ‘

0’

or ‘

1’

, and b corresponds to a polarization of the propagating density as it passes through a tuned quantum point contact, ‘

0’

or ‘

1’

, as the electron density passing the electron density through an input end of the device into a tunnel region of the device in one of four possible states for the electrons;

45. The method of encryption according to claim 44, further comprising using one of the spin down state of the electron by applying a negative magnetic field to the electron density as it passes through the quantum point contact, or using the spin up state of the electron by applying a positive magnetic field to the electron density as it passes through the quantum point contact.

46. A method of secure, encrypted communication comprising:

(a) providing a movement of a series of charge carrier densities,

(b) selectively electron spin polarizing some of the charge carrier densities in the series in one spin direction, while not electron spin polarizing in that spin direction the remaining charge carrier densities in the series,

(c) irrespective of electron spin polarization, directing the movement of a portion of the charge carrier densities along a first path, and

(d) irrespective of electron spin polarization, directing movement of a remaining portion of the charge carrier densities along a second path.

47. The method of secure, encrypted communication of claim 46, wherein step (b) comprises leaving the remaining charge carrier densities without electron spin polarization.

48. The method of secure, encrypted communication of claim 46, wherein step (b) comprises providing a quantum point contact and applying a magnetic field at the quantum point contact to those charge carrier densities to be electron spin polarized.

49. The method of secure, encrypted communication of any one of claims 46, 47 or 48, wherein step (c) comprises:

(i) providing a first waveguide, and

(ii) directing the portion of the charge carrier densities along the first waveguide to a first output, and

step (d) comprises;

(i) providing a second waveguide, and

(ii) directing the remaining portion of the charge carrier densities along the second waveguide to a second output.

50. The method of secure, encrypted communication of claim 49, further comprising providing a coupling between the waveguides, and wherein directing the remaining portion of the charge carrier densities along the second waveguide comprises directing the remaining portion from a part of the first waveguide to the second waveguide via the coupling.

51. The method of secure, encrypted communication of claim 50, wherein directing the remaining portion of the charge carrier densities from a part of the first waveguide to the second waveguide comprises applying at least one of an electric and a magnetic bias to the remaining portion.

52. The method of secure, encrypted communication of claim 51, wherein the steps of providing a first waveguide and providing a second waveguide comprises defining the first and the second waveguide in a semiconductor by establishing electrical potentials defining the waveguides, and the step of directing the remaining portion of the charge carrier densities from a portion of the first waveguide to the second waveguide via the coupling comprises providing a tunnel region coupling the waveguides and selectively applying the bias to choose which of the charge carrier densities to direct to the second waveguide via the tunnel region.

53. The method of secure, encrypted communication of claim 46, wherein four output characteristics are produced of the form: