COMPLEMENTARY SOURCE FOLLOWER CIRCUIT CONTROLLED BY BACK BIAS VOLTAGE

• US 20040104760A1
• Filed: 07/13/2003
• Published: 06/03/2004
• Est. Priority Date: 07/22/2002
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Yoshiyuki Ando
• Inventors: Ando, Yoshiyuki
• Granted Patent: US 6,765,430 B2
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H03K 17/08142 in field-effect transistor switches
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

A complementary source follower circuit has an N-channel type transistor and a P-channel transistor. The threshold voltage of each transistor is independently controlled by a back bias voltage control circuit so that the input voltage and the output voltage relationship can be made linear without the use of an additional circuit such as a level shifting circuit. Also, power consumption can be reduced when the circuit is in standby mode by using the back bias voltage control circuit to achieve non-linearity. A back bias voltage control circuit can also be used to control the threshold voltage of a transistor in series with a resistance load to reduce power usage.

Claims

1. A complementary source follower circuit comprising

(A) an N-channel transistor and a P-channel transistor on a substrate, each having a body connected to a body terminal, a gate connected to a gate terminal, a source connected to a source terminal, and a drain connected to a drain terminal;

(B) a control signal line connection from each of said gate terminals to an input terminal;

(C) a control signal line connection from each of said source terminals to an output terminal;

(D) a connection from the drain terminal of said N-channel transistor to a positive terminal of a power supply and a connection from the drain terminal of said P-channel transistor to a negative terminal of a power supply; and

(E) a control signal line connection from a back bias control circuit to each body terminal and to each source terminal, where said back bias control circuit shifts the threshold voltage of at least one of said transistors, wherein there is no control signal line connection from a body terminal to a source terminal, from a body terminal to a drain terminal, or from said back bias circuit to a drain terminal.

2. A complementary source follower circuit according to claim 1 wherein said substrate is an SOI.

3. A complementary source follower circuit according to claim 1 wherein said substrate is single crystal silicon.

4. A complementary source follower circuit according to claim 3 wherein said substrate is N-doped.

5. A complementary source follower circuit according to claim 3 wherein said substrate is P-doped.

6. A complementary source follower circuit according to claim 3 wherein said substrate is undoped.

7. A complementary source follower circuit according to claim 1 wherein at least some of the signals to said input terminal are analog.

8. A complementary source follower circuit according to claim 1 that includes a level voltage shift circuit for shifting the input voltage to at least one of said transistors.

9. A complementary source follower circuit according to claim 1 wherein said back bias control circuit independently shifts the threshold voltage of each of said transistors.

10. A complementary source follower circuit according to claim 9 wherein said back bias control circuit shifts the threshold voltage of at least one transistor to achieve linearity when said complementary source follower circuit is in active mode.

11. A complementary source follower circuit according to claim 9 wherein said back bias control circuit shifts the threshold voltage of at least one transistor to achieve non-linearity when said complementary source follower circuit is in standby mode.

12. A method of eliminating a dead gap in a complementary source follower circuit according to claim 1 comprising shifting the threshold voltage of at least one of said transistors to achieve linearity when said complementary source follower circuit is in active mode.

13. A method according to claim 12 wherein power loss in standby mode is reduced by shifting the threshold voltage of at least one of said transistors to create a dead gap when said complementary source follower circuit is in standby mode.

14. An LSI having thereon at least one complementary source follower circuit according to claim 1.

15. An LSI according to claim 14 wherein at least one complementary source follower circuit functions as an output buffer.

21. A source follower circuit according to claim 1 wherein said back bias control circuit alternatively applies the voltages of Vss or Vcc to each body terminal.

16. A complementary source follower circuit for processing an analog signal comprising

(A) an N-channel type transistor and a P-channel transistor on a substrate, each having a body connected to a body terminal, a gate connected to a gate terminal, a source connected to a source terminal, and a drain connected to a drain terminal, where there is no connection from a body terminal to a source terminal or from a body terminal to a drain terminal;

(B) a control signal line connection from each of said gate terminals to an input terminal;

(C) a control signal line connection from each of said source terminals to an output terminal;

(D) a connection from the drain terminal of said N-channel transistor to a positive terminal of a power supply and a connection from the drain terminal of said P-channel transistor to a negative terminal of a power supply; and

(E) a control signal line connection from a back bias control circuit to each body terminal and to each source terminal, where said back bias control circuit independently shifts the threshold voltage of each of said transistors to achieve linearity when said complementary source follower circuit is in active mode and to achieve non-linearity when said complementary source follower circuit is in standby mode, and there is no control signal line connection from said back bias circuit to a drain terminal.

17. A complementary source follower circuit according to claim 16 wherein said substrate is an SOI.

18. A complementary source follower circuit according to claim 16 wherein said substrate is single crystal silicon.

19. A source follower circuit comprising

(A) a transistor having a body connected to a body terminal, a gate connected to a gate terminal, a source connected to a source terminal, and a drain connected to a drain terminal, where there is no connection from a body terminal to a source terminal or from a body terminal to a drain terminal;

(B) a control signal line connection from said gate terminal to an input terminal;

(C) a resistance load having a first terminal and a second terminal;

(D) a control signal line connection from said source terminal and from said first terminal to an output terminal;

(E) a power supply having two terminals;

(F) a connection from the drain terminal of said transistor to one terminal of said power supply and a connection from said second terminal to the other terminal of said power supply; and

(G) a control signal line connection from a back bias control circuit to said body terminal and to said source terminal, where said back bias control circuit independently controls the threshold voltage of said transistor to reduce power usage by said circuit, and there is no control signal line connection from said back bias circuit to a drain terminal.

20. A source follower circuit according to claim 19 wherein said transistor is an N-channel transistor.