Integrated circuit arrangement with a cascoded current source and an adjusting circuit for adjusting the operating point of the cascoded current source

• US 20040104765A1
• Filed: 05/27/2003
• Published: 06/03/2004
• Est. Priority Date: 05/27/2002
• Status: Active Grant

• Current Assignee: National Semiconductor Germany AG (Texas Instruments, Inc.)
• Original Assignee: Xignal Technologies AG (Texas Instruments, Inc.)
• Inventors: Ebner, Christian
• Granted Patent: US 6,798,279 B2
• Time in Patent Office: Days
• US Class Current: 327/543
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

An integrated circuit arrangement is provided according to the present invention, including a cascoded current source (10) and an adjusting circuit (20) for adjusting the operating point (Vg1, Vg2, Vx) of the cascoded current source (10) by providing gate potentials (Vg1, Vg2) for current source FETs (Q1, Q2), the adjusting circuit having: a reference stage, formed by a pair of reference FETs (M2, M1), which are supplied with reference currents (Iref1, Iref2) in such a way that the current densities in the reference FETs (M2, M1) differ by a predetermined factor (N²), for providing reference gate potentials (Vgs1, Vgs2) at the gates of the reference FETs (M2, M1); a processing stage, for providing an adjustment potential (Vgt1+V1) on the basis of the predetermined factor (N²), which is equal to the effective control voltage (Vgt1) of the first reference FET (M2) plus a predetermined additional voltage (V1), and an output FET (M9), which is connected on the source side to the adjustment potential (Vgt1+V1). Therefore, the present invention provides a circuit for operating point adjustment of a cascoded FET current source, independent of process and temperature variations, which may be used in many highly integrated analog circuits and maximizes the dynamic range.

Claims

1. An integrated circuit arrangement, including

a cascaded current source (10) for providing an output current (Iout), which is formed by a series circuit of a first current source FET (Q1), connected on the source side to a supply voltage (GND) and a second current source FET (Q2), situated as a cascade, which are operated in saturation, and

an adjusting circuit (20) for adjusting the operating point (Vg1, Vg2, Vx) of the cascoded current source (10) by providing a first gate potential (Vg1) and a second gate potential (Vg2) for the first current source FET (Q1) and/or the second current source FET (Q2),

wherein the adjusting circuit has:

a reference stage, which is formed by a pair of a first reference FET (M2) and a second reference FET (M1), which are operated in saturation and connected on the source side to the supply voltage (GND) and which are supplied with a first reference current (Iref1) and a second reference current (Iref2), respectively, the reference FETs (M2, M1) being dimensioned in such a way and the reference currents (Iref1, Iref2) being selected in such a way that the current density in the second reference FET (M1) differs by a predetermined factor (N²) from the current density in the first reference FET (M2), for providing a first reference gate potential (Vgs1) and a second reference gate potential (Vgs2) at the gate of the first reference FET (M2) and/or at the gate of the second reference FET (M1),

a processing stage, into which the first reference gate potential (Vgs1) and the second reference gate potential (Vgs2) are input, for providing an adjustment potential (Vgt1+V1) on the basis of the predetermined factor (N²), which is equal to the effective control voltage (Vgt1) of the first reference FET (M2) plus a predetermined additional voltage (V1), and

an output FET (M9), operated in saturation, which is connected on the source side to the adjustment potential (Vgt1+V1) and is dimensioned in such a way that the current density in the output FET (M9) is at least approximately equal to the current density in the second current source FET (Q2),

the potential at the gate of the output FET (M9) being provided as the second gate potential (Vg2).

2. The circuit arrangement according to claim 1, wherein the predetermined factor (N²) in the reference stage is in the range from approximately 2 to 100.

3. The circuit arrangement according to claim 1, wherein the first reference current (Iref1) and the second reference current (Iref2) in the reference stage are at least approximately equal.

4. The circuit arrangement according to claim 1, wherein the first reference FET (M2) is an at least approximately equally dimensioned replication of the first current source FET (Q1).

5. The circuit arrangement according to claim 1, wherein the processing stage has:

a voltage-current converter for converting the first reference gate potential (Vgs1) and the second reference gate potential (Vgs2) into currents, whose values are each proportional to the reference gate potentials (Vgs1, Vgs2), reduced by a threshold voltage (Vth), and differ from one another as a function of the predetermined factor (N 2),

a current mirror for weighted subtraction of these currents and for providing a result current corresponding to the result of the weighted subtraction, whose value is proportional to the effective control voltage (Vgt1), and

a current-voltage converter for converting the result current into a voltage which is equal to the effective control voltage (Vgt1) of the first reference FET (M2) and for adding the predetermined additional voltage (V1) to this voltage, or for converting the result current, increased by an additional current (Iref3), into a voltage which is equal to the effective control voltage (Vgt1) of the first reference FET (M2) plus a predetermined additional voltage (V1), in order to provide the adjustment potential (Vgt1+V1).

6. The circuit arrangement according to claim 5, wherein the processing stage has:

a parallel arrangement of a first processing FET (M4) and a second processing FET (M3), which are each connected on the source side to the supply potential (GND) via a resistor (R) and are operated in saturation, the current density provided in the processing FETs (M4, M3) being at least approximately equal in order to provide processing currents which are each in a fixed ratio to the effective control voltage (Vgt1) of the first reference FET (M2) and are in a fixed ratio to one another which corresponds to the square root of the predetermined factor (N²),

a cascoded current mirror (M5, M6, M7, M8) for weighted subtraction of the processing currents in such a way that a result current is provided at an output of the current mirror which is in a fixed ratio to the effective control voltage (Vgt1) of the first reference FET (M2),

an addition node (22) for adding the result current and a predetermined additional current (Iref3), and

a resistor (R), via which the added current is guided in order to provide the adjustment potential (Vgt1+V1) as the voltage drop at the resistor.

7. The circuit arrangement according to claim 1, wherein the output FET (M9) is connected on the source side via a resistor (R) to the supply potential (GND), at which the adjustment potential (Vgt1+V1) drops, a component of a current flow which corresponds to the predetermined additional voltage (V1) being guided through the resistor (R) via the output FET (M9).