High dynamic linearity current-mode digital-to-analog converter architecture

• US 20040104832A1
• Filed: 09/02/2003
• Published: 06/03/2004
• Est. Priority Date: 08/30/2002
• Status: Active Grant

• Current Assignee: EDGEWATER WIRELESS SYSTEMS INC.
• Original Assignee: Engim, Inc.
• Inventors: Bugeja, Alexander
• Granted Patent: US 6,906,652 B2
• Time in Patent Office: Days
• US Class Current: 341/145
• CPC Class Codes: H03M 1/0643 in the spatial domain
• CPC Class Codes: H03M 1/682 both converters being of the unary decoded type
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals

Abstract

The present invention dramatically reduces dynamic mismatches between the different current segments of a segmented current-mode DAC. By providing substantially the same local architecture for each of the individual current segments, parasitic effects of any physical realization can be controlled. In one embodiment, the most-significant-bit (MSB) current segments and the least-significant-bit (LSB) current segments each have the same number of multiple internal current branches. In the MSB segments, the multiple internal current branches are combined at a source node; whereas, in the LSB segment, a portion of the segment current is dumped, or wasted, through at least some of the internal current branches.

Claims

1. A segmented, current-mode Digital-to-Analog Converter (DAC) comprising:

a summing node;

a dump node;

a control input;

a Most Significant Bit (MSB) current leg coupled to the summing node, the MSB current leg conducting a first current relative to the summing node in response to the control input; and

a Least Significant Bit (LSB) current leg coupled to the summing node, the LSB current leg conducting a second current relative to the summing node in response to the control input and conducting current relative to the dump node.

2. The DAC of claim 1, wherein the summing node comprises a positive source node and a negative source node.

3. The DAC of claim 1, further comprising a second MSB current leg coupled to the summing node, the second MSB segment conducting a first current in response to the control input.

4. The DAC of claim 1, wherein the dump node is coupled to an electrical ground.

5. The DAC of claim 1, wherein the dump node is coupled to an electrical power supply.

6. The DAC of claim 1, further comprising a decoder receiving a digital word and generating the control input in response thereto.

7. The DAC of claim 1, wherein the MSB current leg and the LSB current leg have substantially the same internal architecture, but for the dump node connection.

8. The DAC of claim 1, wherein:

the MSB current leg comprises;

a first plurality of current branches coupled together at one end, and coupled to the summing node at the other end, each current branch conducting a respective portion of the first current; and

the LSB current leg comprises;

a second plurality of current branches coupled together at one end, at least one current branch coupled to the summing node at its other end, the remaining current branches coupled to the dump node at their other ends, each current branch conducting a respective portion of the first current.

9. The DAC of claim 8, wherein at least one of the MSB current source and the LSB current source comprises a transistor.

10. The DAC of claim 9, wherein the transistor is selected from the group including:

a Field-Effect Transistor (FET);

a p-type FET;

an n-type FET;

a junction FET;

a metal-oxide-semiconductor FET; and

a bipolar junction transistor.

11. The DAC of claim 8, wherein the first and second pluralities of current branches have the same number of respective current branches.

12. The DAC of claim 8, wherein each current branch of the first plurality of current branches comprises a respective MSB switch coupled between the summing node and the MSB current source, the MSB switch coupling the summing node to the MSB current source in response to the control input.

13. The DAC of claim 12, wherein the MSB switch comprises a transistor switch.

14. The DAC of claim 13, wherein the transistor is selected from the group including:

a Field-Effect Transistor (FET);

a p-type FET;

an n-type FET;

a junction FET;

a metal-oxide-semiconductor FET; and

a bipolar junction transistor.

15. The DAC of claim 8, wherein the MSB current source comprises an MSB cascode device.

16. The DAC of claim 8, wherein each current branch of the second plurality of current branches comprises a respective LSB switch coupled between the respective node and the LSB current source, the LSB switch coupling the respective node to the LSB current source in response to the control input.

17. The DAC of claim 8, wherein the LSB current source comprises an LSB cascode device.

18. The DAC of claim 8, wherein the LSB switch comprises a transistor.

19. The DAC of claim 18, wherein the transistor is selected from the group including:

a Field-Effect Transistor (FET);

a p-type FET;

an n-type FET;

a junction FET;

a metal-oxide-semiconductor FET; and

a bipolar junction transistor.

20. A digital-to-analog converting method for generating a linear, high-speed analog output signal comprising:

receiving a control input;

conducting in a Most Significant Bit (MSB) current leg, a first current relative to a summing node in response to receiving the control input;

conducting in a Least Significant Bit (LSB) current leg, a second current relative to the summing node in response to receiving the control input; and

conducting in the LSB current leg, a current relative to a dump node.

21. The digital-to-analog converting method of claim 20, wherein the first and second currents are differential-mode currents.

22. The digital-to-analog converting method of claim 20, further conducting, in response to the control input, a first current in a second MSB current leg, the second MSB current leg also coupled between a source node and a summing.

23. The digital-to-analog converting method of claim 20, wherein dumping a portion of the second current comprises dumping the portion of current to electrical ground.

24. The digital-to-analog converting method of claim 20, wherein dumping a portion of the second current comprises dumping the portion of current to a supply.

25. The digital-to-analog converting method of claim 20, further comprising:

receiving a digital word;

decoding the received digital word; and

generating a control input in response thereto.

26. The digital-to-analog converting method of claim 20, further comprising:

providing an MSB current source coupled between the source node and the summing node;

dividing the first current across a first plurality of current branches coupled between the source node and the MSB current source; and

providing an LSB current source coupled between the source node and the summing node; and

dividing the second current across a second plurality of current branches, at least one of the second plurality of current branches coupled between the source node and the LSB current source, the remaining current branches of the second plurality of current branches coupled between the dump node and the LSB current source.

27. The digital-to-analog converting method of claim 26, wherein providing at least one of the MSB current source and the LSB current source comprises providing a suitably biased transistor.

28. The digital-to-analog converting method of claim 27, wherein the transistor is selected from the group including:

a Field-Effect Transistor (FET);

a p-type FET;

an n-type FET;

a junction FET;

a metal-oxide-semiconductor FET; and

a bipolar junction transistor.

29. The digital-to-analog converting method of claim 26, wherein the first and second pluralities of current branches have the same number of respective current branches.

30. The digital-to-analog converting method of claim 26, further comprising:

switching the first plurality of current branches between a conducting and nonconductive mode responsive to the control input; and

switching the second plurality of current branches between a conducting and non-conductive mode responsive to the control input.

31. The digital-to-analog converting method off claim 30, wherein switching the first and second pluralities of current segments comprises operating a transistor as a switch.

32. The digital-to-analog converting method of claim 31, wherein the transistor is selected from the group including:

a Field-Effect Transistor (FET);

a p-type FET;

an n-type FET;

a junction FET;

a metal-oxide-semiconductor FET; and

a bipolar junction transistor.

33. The digital-to-analog converting method of claim 26, further comprising:

coupling, in series with the MSB switch and the MSB current source, an MSB cascode device.

34. The digital-to-analog converting method of claim 26, further comprising:

coupling, in series with the LSB switch and the LSB current source, an LSB cascode device.

35. A digital-to-analog converter comprising:

means for receiving a control input;

means for conducting, in response to the received control input, a first current in a Most Significant Bit (MSB) current leg;

means for conducting, in response to the received control input, a second current in a Least Significant Bit (LSB) current leg; and

means for dumping a portion of the second current; and

means for combining the first current, the second current, and the dump current.