Erasing method for p-channel NROM

• US 20040105313A1
• Filed: 11/12/2003
• Published: 06/03/2004
• Est. Priority Date: 09/28/2001
• Status: Abandoned Application

• Current Assignee: Han-Chao Lai, Hung-Sui Lin, Tao-Cheng Lu
• Original Assignee: Han-Chao Lai, Hung-Sui Lin, Tao-Cheng Lu
• Inventors: Lu, Tao-Cheng, Lin, Hung-Sui, Lai, Han-Chao
• Application Number:
  US10/712,586
• Publication Number:
  US 20040105313A1
• Time in Patent Office: Days
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

An erasing method for a p-channel nitride read only memory. The method is used for a p-channel nitride read only memory having charges stored in a charge-trapping layer. A positive voltage is applied to the control gate and a negative voltage to the drain; also, the source is floating and the n-well is grounded. The voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.

Claims

1. An erasing method for a p-channel nitride read only memory, wherein the p-channel nitride read only memory has a control gate, a drain and a source, and formed in a n-well, the erasing method comprising:

applying a positive voltage to the control gate and a negative voltage to the drain;

floating the source; and

grounding the n-well.

2. The erasing method of claim 1, wherein a voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.

3. The erasing method of claim 1, wherein the voltage difference is not sufficient to open a channel of the p-channel nitride read only memory.

4. An erasing method for a p-channel nitride read only memory, wherein the p-channel nitride read only memory has a control gate, a drain and a source, and formed in a n-well, the erasing method comprising:

applying a first voltage to the control gate and a second voltage to the drain;

applying a third and a fourth voltages to the source and the n-well respectively, wherein a voltage difference between the first voltage the second voltage is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.

5. The erasing method of claim 4, wherein the first voltage is a positive voltage.

6. The erasing method of claim 4, wherein the second voltage is a negative voltage.

7. The erasing method of claim 4, wherein the third voltage is to float the source.

8. The erasing method of claim 4, wherein the fourth voltage is a ground voltage.

9. The erasing method of claim 4, wherein the voltage difference is not opened a channel of the p-channel nitride read only memory.