Measurement architecture to obtain per-hop one-way packet loss and delay in multi-class service networks

• US 20040105391A1
• Filed: 11/29/2002
• Published: 06/03/2004
• Est. Priority Date: 11/29/2002
• Status: Active Grant

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Alcatel-Lucent SA (Nokia Corporation)
• Inventors: Charcranoon, Saravut
• Granted Patent: US 7,292,537 B2
• Time in Patent Office: Days
• US Class Current: 370/252
• CPC Class Codes: H04L 43/0829 Packet loss
• CPC Class Codes: H04L 43/0852 Delays
• CPC Class Codes: H04L 43/106 using time related information in packets, e.g. by adding timestamps

Abstract

An architecture for measurement of per-hop, one-way delay includes a input observation circuit (24) at the input interface of a node (12) and a output observation circuit (26) at the output interface (16) of a node (12). The input observation circuit (24) copies and time stamps the headers of incoming packets, and filters packets according to an aggregate definition. Similarly, the output observation circuit (26) copies and time stamps the headers of outgoing packets, and filters packets according to the aggregate definition. The incoming and outgoing traces are correlated to calculate a delay measurement. A packet loss measurement uses input observation circuits (72a and 72b) at the input interfaces (14) of upstream and downstream nodes (20 and 22) and an output observation circuit 74 at the output interface (16) of the upstream node. The observation circuits (72a, 72b and 74) determine the number of lost packets across a node and between nodes, according to an aggregate definition.

Claims

1. A method of measuring per-hop, one-way performance characteristics in a packet-based network, comprising the steps of:

defining an aggregate specification for specifying a type of packet to be included in a measurement;

generating packet headers with associated timestamps for packets flowing through a first point;

generating packet headers with associated timestamps for packets flowing through a second point;

calculating one or more performance measurements responsive to the timestamps associated with corresponding packet headers according to the aggregate specification.

2. The method of claim 1 and further comprising the step of filtering packet headers responsive to the aggregate specification.

3. The method of claim 1 wherein said first point is the input interface of a node and the second point is the output interface of the node and wherein said calculating step comprises the step of calculating a delay measurement.

4. The method of claim 1 and further comprising the step of generating packet headers with associated timestamps for packets flowing through a third point.

5. The method of claim 4 and further comprising the step of filtering packet headers at said first, second and third points according to the aggregate specification.

6. The method of claim 4 wherein said first point is the input interface of a first node, the second point is the output interface of the first node, and the third point is the input interface of a second node and wherein said calculating step comprises the step of calculating a packet loss measurement.

7. Circuitry for measuring per-hop, one-way performance characteristics in a packet-based network, comprising:

circuitry for generating packet headers with associated timestamps for packets flowing through a first point;

circuitry for generating packet headers with associated timestamps for packets flowing through a second point;

circuitry for calculating one or more performance measurements responsive to the timestamps associated with corresponding packet headers according to a predefined aggregate specification.

8. The circuit of claim 7 and further comprising circuitry for filtering packet headers responsive to the aggregate specification.

9. The circuit of claim 7 wherein said first point is the input interface of a node and the second point is the output interface of the node and wherein said calculating circuitry comprises circuitry for calculating a delay measurement.

10. The circuit of claim 7 and further comprising circuitry for generating packet headers with associated timestamps for packets flowing through a third point.

11. The circuit of claim 10 and further comprising circuitry for filtering packet headers at said first, second and third points according to the aggregate specification.

12. The circuit of claim 10 wherein said first point is the input interface of a first node, the second point is the output interface of the first node, and the third point is the input interface of a second node and wherein said calculating circuitry comprises circuitry for calculating a packet loss measurement.