[PIXEL STRUCTURE AND FABRICATING METHOD THEREOF]

• US 20040106238A1
• Filed: 08/29/2003
• Published: 06/03/2004
• Est. Priority Date: 10/03/2002
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Lai, Han-Chung
• Granted Patent: US 6,875,645 B2
• Time in Patent Office: Days
• US Class Current: 438/151
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A method of fabricating a pixel structure. A gate is formed over the substrate and then an insulation layer is formed over the substrate covering the gate. A channel layer is formed over the insulation layer above the gate. A pair of source/drain terminals is formed over the channel layer, thereby producing a thin film transistor on the substrate. A passivation layer is formed over the substrate covering the thin film transistor. A photoresist layer is formed over the passivation layer. Using the gate, the source/drain terminals as a mask, a back exposure process and a photoresist development are sequentially conducted to pattern the photoresist layer. Using the patterned photoresist layer as an etching mask, the passivation layer and the insulation layer are etched to expose a sidewall of the drain terminal. The photoresist layer is removed. A pixel electrode is formed over the passivation layer such that the pixel electrode and the drain terminal are electrically connected through the sidewall of the drain terminal.

Claims

1. A method of forming a pixel structure, comprising the steps of:

forming a gate and a scan line having connection with the gate over a substrate;

forming an insulation layer over the substrate covering the gate and the scan line;

forming a channel layer over the insulation layer above the gate;

forming source/drain terminals over the channel layer and a data line having connection with one of the source/drain terminals over the insulation layer, wherein the gate, the channel layer and the source/drain terminal together constitute a thin film transistor;

forming a passivation layer over the substrate covering the thin film transistor;

forming a photoresist layer over the passivation layer;

conducting a back exposure process using the source/drain terminals, the scan line and the data line as a mask and chemically developing the photoresist layer to form a patterned photoresist layer;

etching the passivation layer and the insulation layer using the patterned photoresist layer as an etching mask to expose a sidewall of the source/drain terminal;

removing the patterned photoresist layer; and

forming a pixel electrode over the passivation layer, wherein the pixel electrode and the drain terminal are electrically connected through the sidewall of the drain terminal.

2. The method of claim 1, wherein before forming the pixel electrode, further includes forming an opening that exposes the drain terminal in the passivation layer such that the pixel electrode and the drain terminal are electrically connected through conductive material within the opening as well as the sidewall of the drain terminal.

3. The method of claim 1, wherein the step of forming the source/drain terminals further includes forming a conductive layer over a neighboring scan line next to the original scan line such that the conductive layer, the neighboring scan line and the insulation layer between the conductive layer and the neighboring scan line together form a pixel storage capacitor.

4. The method of claim 3, wherein the pixel electrode and a sidewall of the conductive layer are electrically connected.

5. The method of claim 1, wherein the data line extends towards the edge of the substrate and connects with a patterned metallic pad such that the pixel electrode and a sidewall of the metallic pad are electrically connected.

6. The method of claim 1, wherein the scan line extends towards the edge of the substrate and connects with a patterned metallic pad such that the pixel electrode and a sidewall of the metallic pad are electrically connected.

7. The method of claim 1, wherein after the step of forming a channel layer over the insulation layer, further includes forming an ohmic contact layer over the channel layer.

8. The method of claim 1, wherein after the step of forming a channel layer over the insulation layer, further includes forming an etching stop layer over the channel layer.

9. A method of forming a pixel structure, comprising the steps of:

forming a gate and a scan line having connection with the gate over a substrate;

forming an insulation layer over the substrate covering the gate and the scan line;

forming a channel material layer over the insulation layer;

forming a metallic layer over the channel layer;

forming a patterned first photoresist layer over the metallic layer;

patterning the metallic layer using the first photoresist layer as a mask to form a data line and a source/drain metallic layer;

patterning the channel material layer using the first photoresist layer as a mask to form a channel layer;

patterning the source/drain metallic layer using the first photoresist layer as a mask to form source/drain terminals, wherein the source terminal and the data line are electrically connected, and the gate, the channel layer and the source/drain terminals together constitute a thin film transistor;

removing the first photoresist layer;

forming a passivation layer over the substrate covering the thin film transistor;

forming a second photoresist layer over the passivation layer;

conducting a back exposure process using the gate, the source/drain terminals, the scan line and the data line as a mask and chemically developing the second photoresist layer to form a patterned second photoresist layer;

patterning the passivation layer and the insulation layer using the patterned second photoresist layer as a mask to expose a sidewall of the source/drain terminal;

removing the patterned second photoresist layer; and

forming a pixel electrode over the passivation layer, wherein the pixel electrode and the drain terminal are electrically connected through a sidewall of the drain terminal.

10. The method of claim 9, wherein before forming the pixel electrode, further includes forming an opening that exposes the drain terminal in the passivation layer such that the pixel electrode and the drain terminal are electrically connected a through conductive material within the opening as well as the sidewall of the drain terminal.

11. The method of claim 9, wherein the step of forming the source/drain terminals further includes forming a conductive layer over a neighboring scan line next to the original scan line such that the conductive layer, the neighboring scan line and the insulation layer between the conductive layer and the neighboring scan line together form a pixel storage capacitor.

12. The method of claim 11, wherein the pixel electrode and a sidewall of the conductive layer are electrically connected.

13. The method of claim 9, wherein the data line extends towards the edge of the substrate and connects with a patterned metallic pad such that the pixel electrode and a sidewall of the metallic pad are electrically connected.

14. The method of claim 9, wherein the scan line extends towards the edge of the substrate and connects with a patterned metallic pad such that the pixel electrode and a sidewall of the metallic pad are electrically connected.

15. The method of claim 9, wherein the step of patterning the source/drain terminals and the channel layer using the first photoresist layer includes the sub-steps of:

forming a patterned first photoresist layer over the metallic layer, wherein the first photoresist layer has a smaller thickness over the area above the gate than the area above the source/drain terminals and the data line;

conducting a first etching step to pattern the metallic layer into the data line and the source/drain metallic layer;

conducting a second etching step to pattern the channel material layer into the channel layer and removing a definite thickness off the first photoresist layer so that the source/drain metallic layer above the gate is exposed; and

conducting a third etching step to pattern the source/drain metallic layer into a source/drain terminal and removing a definite thickness off the channel layer.

16. The method of claim 9, wherein after the step of forming a channel layer over the insulation layer, further includes forming an ohmic contact layer over the channel layer.

17. A pixel structure over a substrate, the pixel structure comprising:

a thin film transistor over the substrate, the thin film transistor having a gate, a channel layer and a pair of source/drain terminals;

a scan line over the substrate, the scan line and the gate being electrically connected;

a data line over the substrate, the data line and the source terminal being electrically connected;

an insulation layer over the substrate only in areas having the gate, the source/drain terminals, the data line and the scan line thereon, and the insulation layer covering the gate and the scan line;

a passivation layer over the substrate only in areas having the gate, the source/drain terminals, the data line and the scan line, and the passivation layer covering the source/drain terminals and the data line, wherein a sidewall of the source/drain terminal is exposed; and

a pixel electrode over the substrate, the pixel electrode being positioned close to the thin film transistor such that the pixel electrode and a sidewall of the drain terminal of the thin film transistor are electrically connected.

18. The pixel structure of claim 17, wherein the pixel structure further include a conductive structure within the passivation layer such that the pixel electrode and the drain terminal are electrically connected through the conductive structure as well as the sidewall of the drain terminal.

19. The pixel structure of claim 17, wherein the pixel structure further include a conductive layer over a scan line neighboring the original scan line such that the conductive layer, the neighboring scan line and the insulation layer between the conductive layer and the neighboring scan line together form a pixel storage capacitor.

20. The pixel structure of claim 19, wherein a sidewall of the conductive layer is electrically connected to the pixel electrode.

21. The pixel structure of claim 19, wherein the pixel structure further include a metallic pad near the edge of the substrate such that the metallic pad and the data line are electrically connected and that the pixel electrode and a sidewall of the metallic pad are electrically connected.

22. The pixel structure of claim 19, wherein the pixel structure further include a metallic pad near the edge of the substrate such that the metallic pad and the scan line are electrically connected and that the pixel electrode and a sidewall of the metallic pad are electrically connected.

23. The pixel structure of claim 19, wherein the pixel structure further include an ohmic contact layer over the channel layer.

24. The pixel structure of claim 19, wherein the pixel structure further include an etching stop layer over the channel layer.