Apparatus and method for multi-threaded processors performance control

• US 20040107369A1
• Filed: 11/30/2002
• Published: 06/03/2004
• Est. Priority Date: 11/30/2002
• Status: Active Grant

• Current Assignee: Sony Corporation Of America (Sony Group Corp.)
• Original Assignee: Intel Corporation
• Inventors: Cooper, Barnes, Kobayashi, Grant H.
• Granted Patent: US 7,219,241 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A power management technique uses system management interrupt (SMI) to manage performance states of logical processors in a physical processor. Each logical processor is associated with a virtual performance state and an actual performance state. A request to retrieve or to change the virtual performance state causes the SMI to be generated. The virtual performance state is a state known to an operating system (OS). The actual performance state is a state that the logical processor is operating at.

Claims

1. A method, comprising:

using system management mode (SMM) to manage performance states of two or more logical processors in a physical processor, wherein each of the two or more logical processor is associated with a virtual performance state and an actual performance state, and wherein the SMM is used to access the virtual performance state and the actual performance state.

2. The method of claim 1, wherein the virtual performance state associated with a first logical processor is a performance state reported to an operating system (OS) when the OS requests for the performance state of the first logical processor.

3. The method of claim 2, wherein the actual performance state associated with the first logical processor is a performance state that the first logical processor is actually operating at.

4. The method of claim 3, further comprising:

reading from a status port to retrieve the virtual performance state.

5. The method of claim 4, further comprising:

writing to an update port to update the virtual performance state from an existing virtual performance state to a new virtual performance state.

6. The method of claim 5, wherein writing to the update port to update the virtual performance state from an existing virtual performance state to a new virtual performance state comprises:

determining if it is an increase or a decrease from the existing virtual performance state to the new virtual performance state.

7. The method of claim 6, wherein when it is an increase and the actual performance state associated with the first logical processor is equal to or higher than the new virtual performance state, the actual performance state of the first logical processor remains unchanged.

8. The method of claim 7, wherein when it is an increase and the actual performance state associated with the first logical processor is lower than the new virtual performance state, the actual performance states of the first logical processor and of all other logical processors coupled to the first logical processor are changed to the new virtual performance state.

9. The method of claim 7, wherein when it is a decrease, the actual performance states of the first logical processor and of all other logical processors coupled to the first logical processor are changed to a highest virtual performance state of all the logical processors.

10. The method of claim 6, further comprising:

changing the existing virtual performance state of the first logical processor to the new virtual performance state.

11. A computer readable medium containing executable instructions which, when executed in a processing system, causes the processing system to perform a method comprising:

using system management interrupt (SMI) to retrieve a virtual performance state of a first logical processor and to change the virtual performance state of the first logical processor, wherein the first logical process is included in a physical processor having two or more logical processors, wherein an actual performance state of the first logical processor may be higher than its virtual performance state.

12. The computer readable medium of claim 11, wherein the actual performance state of the first logical processor is changed to a new virtual performance state for the first logical processor when the new virtual performance state is higher than its existing actual performance state.

13. The computer readable medium of claim 12, wherein when the actual performance state of the first logical processor is changed because its new virtual performance state is higher than its existing actual performance state, actual performance states of all other logical processors are also increased to the new virtual performance state of the first logical processor.

14. The computer readable medium of claim 11, wherein the actual performance state of the first logical processor is changed when a new virtual performance state for the first logical processor is lower than its existing virtual performance state.

15. The computer readable medium of claim 14, wherein changing the actual performance state of the first logical processors comprises:

determining a highest virtual performance state of all the logical processors; and

changing the actual performance state of the first logical processor to the highest virtual performance state.

16. The computer readable medium of claim 15, further comprises:

changing actual performance states of all other logical processors to the highest virtual performance state

17. A method, comprising:

using system management interrupt (SMI) to retrieve a virtual performance state of a first logical processor and to change the virtual performance state of the first logical processor, wherein the first logical processor is included in a physical processor having two or more logical processors, wherein an actual performance state that the first logical processor is to operate at can be different from its virtual performance state that is known to an operating system (OS).

18. The method of claim 17, wherein the actual performance state of the first logical processor is selected based on a highest actual performance state of the two or more logical processors.

19. The method of claim 17, wherein the actual performance state of the first logical processor is selected based on a highest virtual performance state of the two or more logical processors.

20. The method of claim 17, wherein the actual performance state of the first logical processor is selected based on a lowest actual performance state of the two or more logical processors.

21. The method of claim 17, wherein the actual performance state of the first logical processor is selected based on a lowest virtual performance state of the two or more logical processors or based on a weighted average of actual performance states of the two or more logical processors.

22. The method of claim 17, wherein the physical processor is to operate at the actual performance state of the first logical processor.

23. A system, comprising:

a physical processor coupled to the memory, the physical processor includes a first logical processor and a second logical processor, wherein performance states of the first logical processor and of the second logical processor are managed by generating a system management interrupt (SMI) and by controlling a virtual performance state register and an actual performance state register associated with each of the logical processors.

24. The system of claim 23, wherein the virtual performance state register of the first logical processor is used to store a virtual performance state of the first logical processor known to an operating system (OS).

25. The system of claim 24, wherein the actual performance state register of the first logical processor is used to store an actual performance state that the first logical processor is actually operating at.

26. The system of claim 25, further comprising a status port to read the virtual performance state register, and an update port to write a desired performance state to the virtual performance state register.

27. The system of claim 26, wherein the SMI is generated when the status port or the update port is accessed.

28. The system of claim 26, wherein when the desired performance state is written into the virtual performance state register of the first logical processor, its existing actual performance state is changed to the desired performance state when (a) the desired virtual performance state is higher than the existing virtual performance state and (b) the existing actual performance state is lower than the desired performance state.

29. The system of claim 28, wherein when the desired performance state is written into the virtual performance state register of the first logical processor, its existing actual performance state is changed a highest virtual performance state of all logical processors when the desired virtual performance state is lower than the existing virtual performance state.

30. The system of claim 29, further comprising changing actual performance states of all the logical processors to the highest virtual performance state when the desired virtual performance state is lower than the existing virtual performance state.