Measuring an error rate in a communication link

• US 20040107391A1
• Filed: 04/09/2003
• Published: 06/03/2004
• Est. Priority Date: 12/03/2002
• Status: Active Grant

• Current Assignee: CommScope Technologies, LLC (CommScope Holding Company, Inc.)
• Original Assignee: ADC Telecommunications Incorporated (TE Connectivity Limited)
• Inventors: Bauman, Donald R.
• Granted Patent: US 6,920,591 B2
• Time in Patent Office: Days
• US Class Current: 714/704
• CPC Class Codes: H04L 1/244 test sequence generators

Abstract

An error rate detector is provided. The error rate detector includes a sequence generator that is adapted to generate a test sequence for comparison with a received sequence. The error rate detector also includes a self synchronization circuit that is responsive to the test sequence received from the sequence generator and the received sequence. The self synchronization circuit is adapted to move the sequence generator to a different point in the sequence based on a measure of mismatches between the test sequence and the received sequence.

Claims

1. An error rate detector comprising:

a memory adapted to receive a sequence transmitted over a communications link and to maintain a running history of a selected size for the received sequence;

a sequence generator adapted to generate an independent test sequence;

a comparator, responsive to the memory and the sequence generator, the comparator adapted to compare the received sequence with the test sequence;

an error rate calculator, responsive to the comparator, for generating a measure of the error rate of the communication link; and

a synchronization monitor, responsive to the comparator, and adapted to provide a signal to reload the sequence generator based on the stored history in the memory when a measure of the synchronization between the received sequence and the test sequence reaches a selected level.

2. The error rate detector of claim 1, wherein the sequence generator comprises a sequence generator that generates one of a pseudorandom bit stream and a sequence of numbers.

3. The error rate detector of claim 2, wherein the memory is sized to store the last N bits of a pseudorandom bit stream of 2^N−

1 bits.

4. The error rate detector of claim 2, wherein the memory is sized to store bits that represent one number in the sequence.

5. The error rate detector of claim 1, wherein the sequence generator comprises a sequence generator that generates a deterministic sequence.

6. The error rate detector of claim 5, wherein the memory stores a number of members of the sequence to allow determination of an expected next member of the sequence.

7. The error rate detector of claim 1, wherein the synchronization monitor comprises a counter that increments when a member of the received sequence matches an expected member of the test sequence and decrements the counter when the member of the received sequence does not match the expected member of the test sequence.

8. The error rate detector if claim 7, wherein the counter increments by one for each match and decrements by two for each mismatch.

9. The error rate detector of claim 1, wherein the synchronization monitor comprises a synchronization monitor that provides the signal to reload the sequence generator when the counter reaches zero.

10. An error rate monitoring system comprising:

a sequence generator that is adapted to produce a sequence and transmit the sequence over a communication link;

a sequence detector, responsive to the sequence received over the communication link, the sequence detector comprising;

a memory adapted to receive the sequence transmitted over the communications link and to maintain a running history of a selected size for the received sequence;

a second sequence generator adapted to generate an independent test sequence;

a comparator, responsive to the memory and the sequence generator, the comparator adapted to compare the received sequence with the test sequence; and

a synchronization monitor, responsive to the comparator, and adapted to provide a signal to reload the sequence generator based on the stored history in the memory when a measure of the synchronization between the received sequence and the test sequence reaches a selected level; and

an error rate calculator, responsive to the comparator of the sequence detector, for generating a measure of the error rate of the communication link.

11. The system of claim 10, wherein the second sequence generator comprises a sequence generator that generates one of a pseudorandom bit stream and a sequence of numbers.

12. The system of claim 11, wherein the memory is sized to store the last N bits of a pseudorandom bit stream of 2^N−

1 bits.

13. The system of claim 11, wherein the memory is sized to store bits that represent one number in the sequence.

14. The system of claim 10, wherein the second sequence generator comprises a sequence generator that generates a deterministic sequence.

15. The system of claim 14, wherein the memory stores a number of bits to allow determination of an expected next member of the sequence.

16. The system of claim 10, wherein the synchronization monitor comprises a counter that increments when a member of the received sequence matches an expected member of the test sequence and decrements the counter when the member of the received sequence does not match the expected member of the test sequence.

17. The system of claim 16, wherein the counter increments by one for each match and decrements by two for each mismatch.

18. The system of claim 15, wherein the synchronization monitor comprises a synchronization monitor that provides the signal to reload the sequence generator when the counter reaches zero.

19. A method for determining an error rate of a communications link, the method comprising:

receiving a deterministic sequence over the communications link;

generating a test sequence;

comparing the received sequence with the test sequence;

calculating an error rate based on the comparison;

determining a synchronization measure between the received sequence and the test sequence; and

when the synchronization measure reaches a selected level, adjusting the generation of the test sequence.

20. The method of claim 19, wherein receiving a deterministic sequence of the communications link comprises receiving a pseudorandom number sequence.

21. The method of claim 19, wherein determining a synchronization measure comprises:

incrementing a counter when a member of the test sequence matches a member of the received sequence; and

decrementing the counter when the member of the test sequence does not match the member of the received sequence.

22. The method of claim 19, and further comprising limiting the counter to a selected maximum level.

23. The method of claim 19, wherein adjusting the generation of the test sequence comprises adjusting the generation of the test sequence when the counter reaches zero.

24. The method of claim 19, wherein adjusting the generation of the test sequence comprises generating a next expected member of the test sequence based on at least one stored member of the received sequence.

25. The method of claim 19, and further comprising memorying a selected portion of the received sequence.

26. The method of claim 19, wherein calculating an error rate comprises calculating a bit error rate.

27. An error rate detector comprising:

a memory adapted to receive a pseudorandom sequence of 2^N−

1 bits transmitted over a communications link and to maintain a running history of N bits for the received sequence;

a sequence generator adapted to independently generate a pseudorandom test sequence;

a comparator, responsive to the memory and the sequence generator, the comparator adapted to compare the received sequence with the test sequence;

an error rate calculator, responsive to the comparator, for generating a measure of the error rate of the communication link;

a synchronization monitor, responsive to the comparator, the synchronization monitor including a counter, the synchronization monitor adapted to increment the counter when a match is detected between the test sequence and the received sequence and is adapted to decrement the counter when a mismatch is detected between the test sequence and the received sequence; and

wherein the synchronization monitor is adapted to provide a signal to reload the sequence generator based on the stored history in the memory when the counter reaches a selected level.

28. An error rate monitoring system comprising:

a sequence generator that is adapted to produce a sequence and transmit the sequence over a communication link; and

a sequence detector, responsive to the sequence received over the communication link, the sequence detector adapted to generate a test sequence for comparison with the received sequence to determine an error rate, wherein the sequence detector further is adapted to self-synchronize the generation of the test sequence to the received sequence when a measure of the synchronization between the received sequence and the test sequence reaches a selected level.

29. An error rate detector, comprising:

a sequence generator that is adapted to generate a test sequence for comparison with a received sequence;

a self-synchronized sequence detector, responsive to the test sequence received from the sequence generator and the received sequence, that is adapted to compare the test and received sequences and to selectively move the sequence generator to a different point in the sequence based on a measure of mismatches between the test sequence and the received sequence; and

an error rate calculator, responsive to the comparison between the test sequence and the received sequence, for generating a measure of the error rate.

30. A method for synchronizing a sequence generator with a remote sequence generator, the method comprising:

receiving a sequence from the remote sequence generator;

comparing a member of the received sequence with a member of a test sequence generated by the sequence generator;

incrementing a counter when the member of the test sequence matches the member of the received sequence;

decrementing the counter when the member of the test sequence does not match the member of the received sequence; and

adjusting the sequence generator based on the received sequence when the counter reaches a selected level.

31. An error rate detector, comprising:

a sequence generator that is adapted to generate a test sequence for comparison with a received sequence; and

a self synchronization circuit, responsive to the test sequence received from the sequence generator and the received sequence, the self synchronization circuit is adapted to move the sequence generator to a different point in the sequence based on a measure of mismatches between the test sequence and the received sequence.