System and method for testing circuitry using an externally generated signature

• US 20040107395A1
• Filed: 12/03/2002
• Published: 06/03/2004
• Est. Priority Date: 12/03/2002
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: Khoche, Ajay, Volkerink, Erik H., Hilliges, Klaus D.
• Granted Patent: US 7,131,046 B2
• Time in Patent Office: Days
• US Class Current: 714/732
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921

Abstract

A system and method enable testing of circuitry using an externally generated signature. An external tester is arranged external to a device under test (DUT). Such external tester is operable to input test data to the DUT, receive output data from the DUT, and generate a signature for at least a portion of such received output data. The external tester compares the generated signature with an expected signature to determine whether the DUT is functioning as expected. If the generated signature fails to match an expected signature, then error data can be written to an error map log. Preferably, further interaction with the DUT is not required after detecting that a generated signature fails to match an expected signature in order to perform such error evaluation. Thus, error evaluation can be performed concurrently with testing of the DUT. Mask data may be stored in a compressed form, and decompressed and used for masking certain non-deterministic output bits in generating the signature.

Claims

1. An off-chip test system comprising:

means for inputting test data to a chip under test;

means for receiving output data from said chip under test responsive to said input test data;

means for generating a signature for at least a portion of said received output data;

means for comparing said generated signature with an expected signature; and

means for storing information to an error map log if said generated signature fails to match with said expected signature.

2. The off-chip test system of claim 1 wherein said means for storing information does not require further interaction with said chip under test after determining that said generated signature fails to match said expected signature for acquiring said information to be stored to said error map log.

3. The off-chip test system of claim 1 wherein said means for generating a signature comprises:

means for generating a signature for a window of said received output data, wherein said window comprises a predetermined number of bits.

4. The off-chip test system of claim 3 wherein said received output data is divided into a plurality of windows, and said means for generating a signature generates a signature for each of said plurality of windows.

5. The off-chip test system of claim 4 wherein said means for comparing comprises:

means for comparing said generated signature for a first window with an expected signature for said first window.

6. The off-chip test system of claim 5 wherein said means for storing information comprises:

means for storing information to an error map log about at least said first window, if said generated signature for said first window fails to match with said expected signature for said first window.

7. The off-chip test system of claim 1 wherein said chip under test comprises circuitry on a semiconductor wafer, and said off-chip test system is arranged external to said wafer.

8. The off-chip test system of claim 1 wherein said chip under test is a packaged chip, and said off-chip test system is arranged external to said packaged wafer.

9. The off-chip test system of claim 1 further comprising:

means for masking at least a portion of said received output data from being used in generating said signature.

10. The off-chip test system of claim 1 further comprising:

means for storing mask data identifying bits of said received output data to be masked, wherein said mask data is compressed.

11. The off-chip test system of claim 10 further comprising:

means for decompressing said mask data.

12. The off-chip test system of claim 10 further comprising:

means for compressing said mask data.

13. The off-chip test system of claim 1 wherein said means for storing information to said error map log stores said at least a portion of said received output data used for generating said signature that fails to match with said expected signature.

14. A system for testing circuitry, said system comprising:

automated test equipment external to said circuitry that is at least temporarily communicatively coupled to said circuitry, wherein said automated test equipment comprises a communicative interface for inputting test data to said circuitry, a communicative interface for receiving output data from said circuitry responsive to said input test data, logic operable to generate a signature for at least a portion of said received output data, compare logic for comparing a generated signature with an expected signature, and logic for storing information to an error map log if a generated signature fails to match an expected signature.

15. The system of claim 14 wherein said circuitry comprises circuitry on a semiconductor wafer.

16. The system of claim 14 wherein said logic for storing said information to an error map log does not require further interaction with said circuitry after detection of a generated signature failing to match an expected signature.

17. The system of claim 14 wherein said information stored to an error map log comprises said at least a portion of the received output data used for generating said signature that failed to match the expected signature.

18. The system of claim 14 wherein said automated test equipment further comprises:

logic for masking at least a portion of the received output data from being used is in generating the signature.

19. The system of claim 18 wherein said automated test equipment further comprises:

data storage communicatively coupled thereto that comprises mask data identifying bits of the received output data to be masked, wherein said mask data is compressed.

20. The system of claim 19 wherein said automated test equipment further comprises:

logic for decompressing the mask data.

21. A method for testing circuitry, said method comprising:

inputting test data to circuitry under test;

receiving, at an external test device, output data from said circuitry under test responsive to said input test data;

generating, at said external test device, a signature for at least a portion of said received output data;

comparing said generated signature with an expected signature to determine whether said circuitry under test functions as expected; and

if said generated signature fails to match with said expected signature, storing information to an error map log, wherein further interaction with said circuitry under test is not required after determining that said generated signature fails to match said expected signature for acquiring said information for storing said information to said error map log.

22. The method of claim 21 further comprising:

dividing said received output data into a plurality of windows, each window comprising a predetermined number of bits, wherein said generating step comprises generating a signature for each of said plurality of windows.

23. The method of claim 22 wherein said comparing step comprises:

comparing said generated signature for a first window with an expected signature for said first window.

24. The method of claim 23 wherein said storing information to an error map log further comprises:

if said generated signature for said first window fails to match with said expected signature for said first window, storing information about at least said first window to said error map log.

25. The method of claim 24 wherein said information about said first window comprises:

the received output data of said first window.