Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI

• US 20040107410A1
• Filed: 11/12/2003
• Published: 06/03/2004
• Est. Priority Date: 03/04/1999
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Misaka, Akio, Odanaka, Shinji
• Granted Patent: US 7,103,870 B2
• Time in Patent Office: Days
• US Class Current: 716/8
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/68 Preparation processes not covered by groups G03F1/20 - G03F1/50
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns. Then, it is determined whether or not optical proximity corrections can be performed effectively using the corrected patterns. If the effectiveness of the corrections is negated, a design rule defining the circuit patterns is changed to make the corrections effective. Thereafter, the initially placed circuit patterns are placed again in accordance with the design rule changed.

Claims

1. A method for planning a layout for an LSI pattern, the LSI pattern including a plurality of circuit patterns, the method comprising the steps of:

designing the circuit patterns;

making an initial placement for the circuit patterns designed;

performing optical proximity corrections on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns;

evaluating effectiveness of the proximity corrections;

if the effectiveness of the corrections is negated,

changing a design rule defining the circuit patterns to make the corrections effective; and

making a re-placement for the initially placed circuit patterns in accordance with the design rule changed.

2. The method of claim 1, wherein the step of forming the corrected patterns includes the step of setting specifications of the corrected patterns to be made, and

wherein the step of evaluating includes the step of changing the specifications to make the corrections effective if the effectiveness of the corrections is negated.

3. The method of claim 1, wherein the step of making the re-placement includes the step of forming multiple re-placement patterns and selecting one of the re-placement patterns that minimizes a total circuit area.

4. The method of claim 1, further comprising the step of defining the design rule such that the circuit patterns can be laid out to make the corrections effective,

wherein the step of making the initial placement or the step of making the re-placement includes the step of placing the circuit patterns in accordance with the design rule.

5. The method of claim 4, wherein the step of defining the design rule includes the step of defining multiple design rules and selecting one of the design rules that minimizes a total circuit area.

6. The method of claim 4, further comprising the steps of:

setting specifications of the corrected patterns to be made;

defining a rule of placing the corrected patterns such that the proximity corrections can be performed effectively using the corrected patterns; and

forming the corrected patterns according to the specifications of the corrected patterns to be made and on the rule of placing the corrected patterns, thereby defining the design rule.

7. The method of claim 6, further comprising the steps of:

evaluating effectiveness of the proximity corrections for the circuit patterns that have been placed in accordance with the design rule; and

modifying the specifications of the corrected patterns to be made or the rule of placing the corrected patterns to make the corrections effective if the effectiveness of the corrections is negated.

8. The method of claim 1, wherein the step of evaluating includes the step of determining whether or not an expected actual size falls within a predetermined range by performing a process simulation including at least one of lithography and etching process steps.

9. The method of claim 8, wherein the lithography process step in the process simulation includes determining whether or not the expected actual size falls within the predetermined range even if an exposure dose or focus has changed so much as to exceed a process margin range.

10. The method of claim 8, wherein in the process simulation, it is determined whether or not an expected size of a transistor in a gate longitudinal direction falls within the predetermined range.

11. The method of claim 8, wherein in the process simulation, it is determined whether or not an expected length of a portion of a transistor gate extending from an active layer in a gate width direction falls within the predetermined range.

12. A method for forming an LSI pattern, the LSI pattern including a plurality of circuit patterns, the method comprising the steps of:

a) designing the circuit patterns;

b) making an initial placement for the circuit patterns designed;

c) performing optical proximity corrections on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns;

d) evaluating effectiveness of the proximity corrections under predetermined process conditions;

if the effectiveness of the corrections is negated,

e) changing a design rule defining the circuit patterns to make the corrections effective;

f) making a re-placement for the initially placed circuit patterns in accordance with the design rule changed;

g) producing a mask using the corrected patterns; and

h) defining the circuit patterns on a semiconductor substrate under the predetermined process conditions by using the mask produced.

13. The method of claim 12, further comprising the steps of:

estimating process yield expectedly attainable when the produced mask is used under the predetermined process conditions after the step g) has been performed; and

if the estimate is short of a target value,

modifying the predetermined process conditions to make the estimate reach the target value and repeatedly performing the steps a) through g).

14. A method for generating mask data for an LSI, comprising the steps of:

a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group will not be changed in shape even when process conditions are modified, while each said corrected pattern of the second group will be changed in shape if the process conditions are modified;

b) generating cell-level optical proximity corrected pattern data from the first group of corrected patterns when the circuit patterns are designed; and

c) generating chip-level optical proximity corrected pattern data from the second group of corrected patterns when chip data is generated from the circuit patterns.

15. The method of claim 14, wherein the step b) includes the steps of:

evaluating effectiveness of optical proximity corrections represented by the cell-level corrected pattern data generated;

if the effectiveness of the corrections is negated,

modifying the cell-level corrected pattern data or circuit patterns corresponding to the cell-level corrected pattern data to make the corrections effective and then re-evaluating effectiveness of the corrections; and

if the effectiveness of the corrections is affirmed,

registering the cell-level corrected pattern data at a cell library.

16. The method of claim 15, wherein if the corrections are effectively applicable to multiple layouts for circuit patterns, the step of evaluating the effectiveness includes the step of selecting one of the layouts that results in a circuit area equal to or smaller than a predetermined value.

17. The method of claim 14, wherein the cell-level corrected pattern data includes serif patterns, hammerhead patterns or in-section patterns.

18. A method for generating mask data for an LSI, comprising the steps of:

a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group will not be changed in shape even when process conditions are modified, while each said corrected pattern of the second group will be changed in shape if the process conditions are modified;

b) setting specifications of cell-level optical proximity corrected patterns to be made for the first group of corrected patterns;

c) designing the circuit patterns;

d) evaluating effectiveness of optical proximity corrections if the cell-level corrected patterns, which have been made for the first group of corrected patterns to the specifications of the cell-level corrected patterns, are used;

if the effectiveness of the corrections is negated,

e) modifying ineffective circuit patterns to make the corrections effective and re-evaluating effectiveness of the corrections;

if the effectiveness of the corrections is affirmed,

f) registering the circuit patterns, belonging to the first and second groups of corrected patterns, at a cell library;

g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library;

h) setting specifications of chip-level optical proximity corrected patterns to be made for the second group of corrected patterns;

i) generating cell-level optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the cell-level corrected patterns; and

j) generating chip-level optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the chip-level corrected patterns.

19. The method of claim 18, wherein if the corrections are effectively applicable to multiple layouts for circuit patterns, the step d) includes the step of selecting one of the layouts that results in a circuit area equal to or smaller than a predetermined value.

20. The method of claim 18, wherein the cell-level corrected pattern data includes serif patterns, hammerhead patterns or in-section patterns.

21. A method for generating mask data for an LSI, comprising the steps of:

a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group will not be changed in shape even when process conditions are modified, while each said corrected pattern of the second group will be changed in shape if the process conditions are modified;

b) setting specifications of cell-level optical proximity corrected patterns to be made for the first group of corrected patterns;

c) designing the circuit patterns;

d) evaluating effectiveness of optical proximity corrections if the cell-level corrected patterns, which have been made for the first group of corrected patterns to the specifications of the cell-level corrected patterns, are used;

if the effectiveness of the corrections is negated, p1 e) modifying ineffective circuit patterns or the specifications of the cell-level corrected patterns corresponding to the circuit patterns to make the corrections effective and re-evaluating effectiveness of the corrections;

if the effectiveness of the corrections is affirmed,

f) registering not only the circuit patterns belonging to the first group of corrected patterns and the specifications of the cell-level corrected patterns corresponding to the circuit patterns, but also the circuit patterns belonging to the second group of corrected patterns at a cell library;

g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library;

h) generating cell-level optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the cell-level corrected patterns; and

i) generating chip-level optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the chip-level corrected patterns.

22. The method of claim 21, wherein if the corrections are effectively applicable to multiple layouts for circuit patterns, the step d) includes the step of selecting one of the layouts that results in a circuit area equal to or smaller than a predetermined value.

23. The method of claim 21, wherein the cell-level corrected pattern data includes serif patterns, hammerhead patterns or in-section patterns.

24. A method for generating mask data for an LSI, comprising the steps of:

a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group is defined by circuit patterns placed to cover multiple layers, while each said corrected pattern of the second group is defined by circuit patterns placed within a single layer;

b) generating interlayer optical proximity corrected pattern data from the first group of corrected patterns in designing the circuit patterns; and

c) generating intralayer optical proximity corrected pattern data from the second group of corrected patterns in generating chip data from the circuit patterns.

25. The method of claim 24, wherein the step b) includes the steps of:

evaluating effectiveness of optical proximity corrections represented by the interlayer corrected pattern data generated;

if the effectiveness of the corrections is negated,

modifying the interlayer corrected pattern data or the circuit patterns corresponding to the corrected pattern data to make the corrections effective and re-evaluating effectiveness of the corrections; and

if the effectiveness of the corrections is affirmed,

registering the interlayer corrected- pattern data at a cell library.

26. The method of claim 25, wherein if the corrections are effectively applicable to multiple layouts for circuit patterns, the step of evaluating includes the step of selecting one of the layouts that results in a circuit area equal to or smaller than a predetermined value.

27. The method of claim 25, wherein the step of evaluating includes the step of determining whether or not an expected actual size falls within a predetermined range by performing a process simulation including at least one of lithography and etching process steps.

28. The method of claim 27, wherein the lithography process step in the process simulation includes determining whether or not the expected actual size falls within the predetermined range even if an exposure dose or focus has changed so much as to exceed a process margin range.

29. The method of claim 27, wherein in the process simulation, it is determined whether or not an expected size of a transistor in a gate longitudinal direction falls within the predetermined range.

30. The method of claim 27, wherein in the process simulation, it is determined whether or not an expected length of a portion of a transistor gate extending from an active layer in a gate width direction falls within the predetermined range.

31. A method for generating mask data for an LSI, comprising the steps of:

a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group is defined by circuit patterns placed to cover multiple layers, while each said corrected pattern of the second group is defined by circuit patterns placed within a single layer;

b) setting specifications of interlayer optical proximity corrected patterns to be made for the first group of corrected patterns;

c) designing the circuit patterns;

d) evaluating effectiveness of optical proximity corrections if the interlayer corrected patterns, which have been made for the first group of corrected patterns to the specifications of the interlayer corrected patterns, are used;

if the effectiveness of the corrections is negated,

e) modifying ineffective circuit patterns to make the corrections effective and re-evaluating effectiveness of the corrections;

if the effectiveness of the corrections is affirmed,

f) registering the circuit patterns, belonging to the first and second groups of corrected patterns, at a cell library;

g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library;

h) setting specifications of intralayer optical proximity corrected patterns to be made for the second group of corrected patterns;

i) generating interlayer optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the interlayer corrected patterns; and

j) generating intralayer optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the intralayer corrected patterns.

32. The method of claim 31, wherein if the corrections are effectively applicable to multiple layouts for circuit patterns, the step d) includes the step of selecting one of the layouts that results in a circuit area equal to or smaller than a predetermined value.

33. The method of claim 31, wherein the specifications of the interlayer corrected patterns to be made are determined by a placement rule defining a layer including a gate of a transistor and another layer including an active region.

34. The method of claim 31, wherein the specifications of the interlayer corrected patterns to be made are determined by a placement rule defining a first interconnection layer and another layer including a contact for electrically connecting the first interconnection layer to a second interconnection layer.

35. The method of claim 31, wherein the step d) includes the step of determining whether or not an expected actual size falls within a predetermined range by performing a process simulation including at least one of lithography and etching process steps.

36. A method for generating mask data for an LSI, comprising the steps of:

a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group is defined by circuit patterns placed to cover multiple layers, while each said corrected pattern of the second group is defined by circuit patterns placed within a single layer;

b) setting specifications of interlayer optical proximity corrected patterns to be made for the first group of corrected patterns;

c) designing the circuit patterns;

d) evaluating effectiveness of optical proximity corrections if the interlayer corrected patterns, which have been made for the first group of corrected patterns to the specifications of the interlayer corrected patterns, are used;

if the effectiveness of the corrections is negated,

e) modifying ineffective circuit patterns or the specifications of the interlayer corrected patterns corresponding to the circuit patterns to make the corrections effective and re-evaluating effectiveness of the corrections;

if the effectiveness of the corrections is affirmed,

f) registering not only the circuit patterns belonging to the first group of corrected patterns and the specifications of the interlayer corrected patterns corresponding to the circuit patterns, but also the circuit patterns belonging to the second group of corrected patterns at a cell library;

g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library;

h) generating interlayer optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the interlayer corrected patterns; and

i) generating intralayer optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the intralayer corrected patterns.

37. The method of claim 36, wherein if the corrections are effectively applicable to multiple layouts for circuit patterns, the step d) includes the step of selecting one of the layouts that results in a circuit area equal to or smaller than a predetermined value.

38. The method of claim 36, wherein the specifications of the interlayer corrected patterns to be made are determined by a placement rule defining a layer including a gate of a transistor and another layer including an active region.

39. The method of claim 36, wherein the specifications of the interlayer corrected patterns to be made are determined by a placement rule defining a first interconnection layer and another layer including a contact for electrically connecting the first interconnection layer to a second interconnection layer.

40. The method of claim 36, wherein the step d) includes the step of determining whether or not an expected actual size falls within a predetermined range by performing a process simulation including at least one of lithography and etching process steps.

41. A method for forming an LSI pattern, comprising the steps of:

a) classifying multiple circuit patterns included in an LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group will not be changed in shape even when process conditions are modified, while each said corrected pattern of the second group will be changed in shape if the process conditions are modified;

b) generating cell-level optical proximity corrected pattern data from the first group of corrected patterns when the circuit patterns are designed;

c) generating chip-level optical proximity corrected pattern data from the second group of corrected patterns when chip data is generated from the circuit patterns;

d) producing a mask using the optical proximity corrected pattern data generated; and

e) defining the circuit patterns on a semiconductor substrate using the mask produced.

42. A method for forming an LSI pattern, comprising the steps of:

a) classifying multiple circuit patterns included in an LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group will not be changed in shape even when process conditions are modified, while each said corrected pattern of the second group will be changed in shape if the process conditions are modified;

b) setting specifications of cell-level optical proximity corrected patterns to be made for the first group of corrected patterns;

c) designing the circuit patterns;

d) evaluating effectiveness of optical proximity corrections if the cell-level corrected patterns, which have been made for the first group of corrected patterns to the specifications of the cell-level corrected patterns, are used;

if the effectiveness of the corrections is negated,

e) modifying ineffective circuit patterns to make the corrections effective and re-evaluating effectiveness of the corrections;

if the effectiveness of the corrections is affirmed,

f) registering the circuit patterns, belonging to the first and second groups of corrected patterns, at a cell library;

g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library;

h) setting specifications of chip-level optical proximity corrected patterns to be made for the second group of corrected patterns;

i) generating cell-level optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the cell-level corrected patterns;

j) generating chip-level optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the chip-level corrected patterns;

k) producing a mask using the optical proximity corrected pattern data generated; and

l) defining the circuit patterns on a semiconductor substrate using the mask produced.

43. A method for forming an LSI pattern, comprising the steps of:

a) classifying multiple circuit patterns included in an LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group will not be changed in shape even when process conditions are modified, while each said corrected pattern of the second group will be changed in shape if the process conditions are modified;

b) setting specifications of cell-level optical proximity corrected patterns to be made for the first group of corrected patterns;

c) designing the circuit patterns;

d) evaluating effectiveness of optical proximity corrections if the cell-level corrected patterns, which have been made for the first group of corrected patterns to the specifications of the cell-level corrected patterns, are used;

if the effectiveness of the corrections is negated,

e) modifying ineffective circuit patterns or the specifications of the cell-level corrected patterns corresponding to the circuit patterns, to make the corrections effective and re-evaluating effectiveness of the corrections;

if the effectiveness of the corrections is affirmed,

f) registering not only the circuit patterns belonging to the first group of corrected patterns and the specifications of the cell-level corrected patterns corresponding to the circuit patterns, but also the circuit patterns belonging to the second group of corrected patterns at a cell library;

g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library;

h) generating cell-level optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the cell-level corrected patterns;

i) generating chip-level optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the chip-level corrected patterns;

j) producing a mask using the optical proximity corrected pattern data generated; and

k) defining the circuit patterns on a semiconductor substrate using the mask produced.

44. A method for forming an LSI pattern, comprising the steps of:

a) classifying multiple circuit patterns included in an LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group is defined by circuit patterns placed to cover multiple layers, while each said corrected pattern of the second group is defined by circuit patterns placed within a single layer;

b) generating interlayer optical proximity corrected pattern data from the first group of corrected patterns in designing the circuit patterns;

c) generating intralayer optical proximity corrected pattern data from the second group of corrected patterns in generating chip data from the circuit patterns;

d) producing a mask using the interlayer and intralayer optical proximity corrected pattern data generated; and

e) defining the circuit patterns on a semiconductor substrate using the mask produced.

45. A method for forming an LSI pattern, comprising the steps of:

a) classifying multiple circuit patterns included in an LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group is defined by circuit patterns placed to cover multiple layers, while each said corrected pattern of the second group is defined by circuit patterns placed within a single layer;

b) setting specifications of interlayer optical proximity corrected patterns to be made for the first group of corrected patterns;

c) designing the circuit patterns;

d) evaluating effectiveness of optical proximity corrections if the interlayer corrected patterns, which have been made for the first group of corrected patterns to the specifications of the interlayer corrected patterns, are used;

if the effectiveness of the corrections is negated,

e) modifying ineffective circuit patterns to make the corrections effective and re-evaluating effectiveness of the corrections;

if the effectiveness of the corrections is affirmed,

f) registering the circuit patterns, belonging to the first and second groups of corrected patterns, at a cell library;

g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library;

h) setting specifications of intralayer optical proximity corrected patterns to be made for the second group of corrected patterns;

i) generating interlayer optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the interlayer corrected patterns;

j) generating intralayer optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the intralayer corrected patterns;

k) producing a mask using the interlayer and intralayer optical proximity corrected pattern data generated; and

l) defining the circuit patterns on a semiconductor substrate using the mask produced.

46. A method for forming an LSI pattern, comprising the steps of:

a) classifying multiple circuit patterns included in an LSI into first and second groups of corrected patterns, where each said corrected pattern of the first group is defined by circuit patterns placed to cover multiple layers, while each said corrected pattern of the second group is defined by circuit patterns placed within a single layer;

b) setting specifications of interlayer optical proximity corrected patterns to be made for the first group of corrected patterns;

c) designing the circuit patterns;

d) evaluating effectiveness of optical proximity corrections if the interlayer corrected patterns, which have been made for the first group of corrected patterns to the specifications of the interlayer corrected patterns, are used;

if the effectiveness of the corrections is negated,

e) modifying ineffective circuit patterns or the specifications of the interlayer corrected patterns corresponding to the circuit patterns to make the corrections effective and re-evaluating effectiveness of the corrections;

if the effectiveness of the corrections is affirmed,

f) registering not only the circuit patterns belonging to the first group of corrected patterns and the specifications of the interlayer corrected patterns corresponding to the circuit patterns, but also the circuit patterns belonging to the second group of corrected patterns at a cell library;

g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library;

h) generating interlayer optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the interlayer corrected patterns;

i) generating intralayer optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the intralayer corrected patterns;

j) producing a mask using the interlayer and intralayer optical proximity corrected pattern data generated; and

k) defining the circuit patterns on a semiconductor substrate using the mask produced.