Methods and systems for cooperative scheduling of hardware resource elements

• US 20040107421A1
• Filed: 12/03/2002
• Published: 06/03/2004
• Est. Priority Date: 12/03/2002
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Westerinen, William J., VoBa, Son, Pierce, Tony Dwayne, See, Valerie R.
• Granted Patent: US 7,337,442 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

Cooperatively scheduling hardware resources by providing information on shared resources within processor packages to the operating system. Logical processors may be included in packages in which some or all processor execution resources are shared among logical processors. In order to better schedule thread execution, information regarding which logical processors are sharing processor execution resources and information regarding which system resources are shared among processor packages is provided to the operating system. Extensions to the SRAT (static resource affinity table) can be used to provide this information.

Claims

1. A method for scheduling processor use on a computer system comprising two or more logical processors sharing common processor execution resources, the method comprising:

storing package information comprising an indication that said first and second logical processors share said common processor execution resources; and

utilizing said package information in scheduling processor use.

2. The method of claim 1, where said package information further comprises information regarding one or more types of said common processor execution resources.

3. The method of claim 2 where said one or more types of said common processor execution resources are selected from among:

I caches, D caches, execution support, on chip main memory, external memory, and power planes.

4. The method of claim 1, where said utilization of said package information in scheduling processor use comprises giving preference to not scheduling two threads that require said common processor execution resources to run simultaneously on said first and second logical processors.

5. The method of claim 1, where said package information is stored in a package affinity structure in a static resource allocation table.

6. The method of claim 5 where said package affinity structure comprises information regarding one or more types of said common processor execution resources.

7. The method of claim 5 where said static resource allocation table further comprises a first architecture state affinity structure for said first logical processor comprising a first package identifier, a second architecture state affinity structure for said second logical processor comprising said first package identifier, and where said package affinity structure comprises said first package identifier.

8. The method of claim 1, where said step of storing package information comprises storing information in an object-oriented schema.

9. A computer-readable medium for scheduling processor use on a computer system comprising two or more logical processors, having stored thereon at least one computer-executable module comprising computer-executable instructions for performing the method of claim 1.

10. A method for scheduling processor use on a computer system comprising two or more processor packages where that at least a first processor package and a second processor package from among said two or more processors packages share common system characteristics, comprising:

storing domain information comprising an indication that said first and second processor packages share said common system characteristics; and

utilizing said domain information in scheduling processor use.

11. The method of claim 10, where said domain information further comprises information regarding one or more types of said common system characteristics.

12. The method of claim 11 where said one or more types of said common system characteristics are selected from among the following:

proximity to a specified memory and proximity to I/O devices.

13. The method of claim 10, where said step of storing domain information comprises storing information in an object-oriented schema.

14. A computer-readable medium for scheduling processor use on a computer system comprising two or more logical processors, having stored thereon at least one computer-executable module comprising computer-executable instructions for performing the method of claim 10.

15. A computer device comprising:

a first logical processor;

a second logical processor sharing common processor execution resources with said first logical processor;

storage for storing information comprising an indication that said first and second logical processors share said common processor execution resources; and

an operating system for scheduling processing said first and said second logical processors based on said stored information.

16. The computer device of claim 15, where said information further comprises information regarding one or more types of said common processor execution resources.

17. The computer device of claim 16, where said one or more types of said common processor execution resources are selected from among:

I caches, D caches, execution support, on chip main memory, external memory, and power planes.

18. The computer device of claim 15, where said utilization of said information in scheduling processor use comprises giving preference to not scheduling two threads that require said common processor execution resources to run simultaneously on said first and second logical processors.

19. The computer device of claim 15, where said storage stores a package affinity structure in a static resource allocation table.

20. The computer device of claim 19 where said package affinity structure comprises information regarding one or more types of said common processor execution resources.

21. The computer device of claim 19 where said static resource allocation table further comprises a first architecture state affinity structure for said first logical processor comprising a first package identifier, a second architecture state affinity structure for said second logical processor comprising said first package identifier, and where said package affinity structure comprises said first package identifier.

22. A computer device for efficient computer processing, comprising:

a first logical processor;

a second logical processor sharing common system characteristics with said first logical processor;

storage for storing domain information comprising an indication that said first and second logical processors share said common system characteristics; and

an operating system for scheduling processing on said first and said second logical processors based on said stored domain information.

23. The computer device of claim 22, where said domain information further comprises information regarding one or more types of said common system characteristics.

24. The computer device of claim 23 where said one or more types of said common system characteristics comprises:

proximity to a specified memory.

25. A processor use scheduler for scheduling processor use on a computer system comprising two or more logical processors sharing common processor execution resources, the scheduler comprising:

means for storing package information comprising an indication that said first and second logical processors share said common processor execution resources; and

means for utilizing said package information in scheduling processor use.