Transient detection circuit

• US 20040109270A1
• Filed: 12/10/2002
• Published: 06/10/2004
• Est. Priority Date: 12/10/2002
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Miller, James W., Stockinger, Michael
• Granted Patent: US 7,209,332 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

A transient detection circuit which may be used in an electrostatic discharge (ESD) clamp circuit. The transient detection circuit includes a filter circuit and an inverter circuit. The voltage switch point of the inverter circuit has a constant voltage offset from one of the nodes. When a filtered voltage level from the filter circuit crosses the voltage switch point of the inverter circuit (indicative of an ESD event), the inverter circuit provides a signal indicating an ESD event.

Claims

1. A transient detection circuit comprising:

a filter circuit coupled to a first node and a second node, the filter circuit having an output; and

an inverter circuit having an input coupled to the output of the filter circuit, the inverter circuit having a voltage switch point that includes an at least substantially constant voltage offset from the first node.

2. The transient detection circuit of claim 1, wherein the filter circuit includes a resistor and a capacitor, the resistor including a first electrode coupled to the first node and a second electrode coupled to the output of the filter circuit, the capacitor including a first electrode coupled to the output and a second electrode coupled to the second node.

3. The transient detection circuit of claim 1 wherein an output of the inverter circuit does not switch output states until the voltage between the first and second nodes exceeds the at least substantially constant voltage offset.

4. The transient detection circuit of claim 1, wherein the inverter circuit includes a first transistor, a second transistor, and a third transistor coupled in series.

5. The transient detection circuit of claim 4, wherein the first transistor includes a first current electrode coupled to the first node and a second current electrode, wherein the second transistor includes a first current electrode coupled to the second current electrode of the first transistor and a second current electrode, and wherein the third transistor includes a first current electrode coupled to the second current electrode of the second transistor and a second current electrode coupled to the second node.

6. The transient detection circuit of claim 5, wherein the second transistor includes a control electrode coupled to the output of the filter circuit.

7. The transient detection circuit of claim 5, wherein the third transistor includes a control electrode coupled to the first node, and wherein the first transistor includes a control electrode coupled to the second current electrode of the first transistor.

8. The transient detection circuit of claim 5 wherein an output of the inverter circuit is connected to the second current electrode of the second transistor and the first current electrode of the third transistor.

9. The transient detection circuit of claim 1, wherein the first node is coupled to receive a first power supply voltage and the second node is coupled to receive a second power supply voltage.

10. The transient detection circuit of claim 9 wherein the first power supply voltage is a positive voltage and the second power supply voltage is ground.

11. The transient detection circuit of claim 9 wherein the first power supply voltage is ground and the second power supply voltage is a positive voltage.

12. The transient detection circuit of claim 1, wherein the transient detection circuit is included as part of a circuit for providing electrostatic discharge (ESD) protection during an ESD event for components in an integrated circuit chip.

13. An integrated circuit chip including the transient detection circuit of claim 1.

14. The integrated circuit chip of claim 13 further comprising:

an ESD protection circuit, the ESD protection circuit including the transient detection circuit.

15. An ESD circuit for providing ESD protection and including the transient detection circuit of claim 1, the ESD circuit further comprising:

a clamp switch coupled to a third node and coupled to a fourth node, the clamp switch providing a discharge path between the third node and the fourth node for current from an ESD event; and

an on-time control circuit having and input coupled to an output of the inverter circuit and an output coupled to the clamp switch for controlling the conductive state of the clamp switch.

16. The ESD circuit of claim 15 wherein the third node is coupled to the first node and the fourth node is coupled to the second node.

17. The transient detection circuit of claim 1 wherein the inverter circuit further includes a current source and a resistor, wherein the at least substantially constant voltage offset includes a voltage drop across the resistor as set by the current source.

18. The transient detection circuit of claim 17 wherein the inverter circuit further includes a transistor, wherein the at least substantially constant voltage offset includes the voltage drop across the resistor and a gate-source voltage of the transistor.

19. The transient detection circuit of claim 17 wherein the resistor is connected to the first node and the current source is connected to the second node.

20. The transient detection circuit of claim 1 wherein the inverter circuit is coupled to the first and second nodes to be powered therefrom.

21. The transient detection circuit of claim 1 wherein the inverter circuit has an output, wherein the output is dependent upon a voltage signal at the first node with respect to the second node having a slew rate greater than a predetermined slew rate.

22. The transient detection circuit of claim 21 wherein the output of the inverter circuit is also dependent upon the first node being at a voltage that is at least higher than a voltage of the second node by the at least substantially constant voltage offset.

23. A circuit for providing electrostatic discharge (ESD) protection during an ESD event for internal components in an integrated circuit, the circuit comprising:

a filter circuit coupled to a first node and to a second node, the filter circuit having an output;

an inverter circuit, having an input coupled to the output of the filter circuit, the inverter circuit having a voltage switch point that includes an at least substantially constant voltage offset from the first node, the inverter circuit having an output that is indicative of a detected ESD event; and

an on-time control circuit coupled to the output of the inverter circuit, the on-time control circuit having an output to provide a signal for making conductive at least one clamp switch to provide a discharge path for current from an ESD event.

24. The circuit of claim 23 wherein the inverter circuit does not switch output states until the voltage between the first and second nodes exceeds the at least substantially constant voltage offset.

25. The circuit of claim 23 wherein the inverter circuit further includes a current source and a resistor, wherein the at least substantially constant voltage offset includes a voltage drop across the resistor as set by the current source.

26. The circuit of claim 23 wherein the inverter circuit further includes a transistor, wherein the at least substantially constant voltage offset includes the voltage drop across the resistor and a gate-source voltage of the transistor.

27. The circuit of claim 23 wherein the inverter circuit is coupled to the first and second nodes to be powered therefrom.

28. An integrated circuit chip including the circuit of claim 23 wherein the first node is coupled to a pad of the integrated circuit chip.

29. The integrated circuit chip of claim 28 wherein the pad is a power supply pad.

30. The circuit of claim 23 wherein a clamp switch of the at least one clamp switch has a first current electrode coupled to the first node and a second current electrode coupled to the second node.

31. A method for detecting a slew rate of a detected voltage between a first node and a second node, the method comprising:

filtering the detected voltage to provide a filtered voltage;

providing the filtered voltage as an input to an inverter circuit which has a voltage switch point that includes an at least substantially constant voltage offset from the first node; and

providing an output from the inverter circuit, wherein the output is a function of the slew rate as indicated by the filtered voltage and the voltage switch point.

32. The method of claim 31 further comprising:

making conductive a clamp switch to discharge current of an ESD event wherein the making conductive is based on the output of the inverter circuit.