Ferroelectric storage apparatus, driving method therefor, and driving circuit therefor
First Claim
1. A driving method for a ferroelectric storage apparatus, characterized by comprising:
- an operation step of applying one of data reading, data re-writing, and data-writing to at least one-selected cell among, a plurality of ferroelectric memory cells formed at the intersections of a plurality of word lines and a plurality of bit lines; and
a disturbance prevention step of applying a voltage to each of the plurality of ferroelectric memory cells in an electric-field direction in which the stored data of each ferroelectric memory cell is not inverted, after the operation step is executed at least once.
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Accused Products
Abstract
A ferroelectric storage apparatus which can prevent disturbance, a driving method therefor, and a driving circuit therefor are provided. In the ferroelectric storage apparatus, an operation step of applying one of data reading, data re-writing, and data writing to at least one selected cell 18a among a plurality of ferroelectric memory cells 18 formed at the intersections of a plurality of word lines 14 and a plurality of bit lines 16 is repeatedly performed. A disturbance prevention step of applying a voltage to each of the plurality of ferroelectric memory cells 18 in an electric-field direction in which the stored data of each ferroelectric memory cell 18 is not inverted is performed after the operation step is executed at least once. With this, a voltage is applied to not selected cells 18b at a certain frequency in an electric-field direction in which they stored data of the not-selected cells is not inverted, and data deterioration is suppressed.
15 Citations
11 Claims
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1. A driving method for a ferroelectric storage apparatus, characterized by comprising:
an operation step of applying one of data reading, data re-writing, and data-writing to at least one-selected cell among, a plurality of ferroelectric memory cells formed at the intersections of a plurality of word lines and a plurality of bit lines; and
a disturbance prevention step of applying a voltage to each of the plurality of ferroelectric memory cells in an electric-field direction in which the stored data of each ferroelectric memory cell is not inverted, after the operation step is executed at least once.- View Dependent Claims (2, 3)
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4. A ferroelectric storage apparatus characterized by comprising:
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a plurality of word lines disposed in parallel to each other;
a plurality of bit lines disposed in parallel to each other and intersecting with the plurality of word lines;
a plurality of ferroelectric memory cells formed at the intersections of the plurality of word lines and the plurality of bit lines;
a word-line driver for driving the plurality of word lines; and
a bit-line driver for driving the plurality of bit lines, and characterized in that the word-line driver and the bit-line driver apply an operation mode of one of data reading, data re-writing, and data writing to at least one selected cell among the plurality of ferroelectric memory cells, and apply a voltage to each of the plurality of ferroelectric memory, cells in an electric-field direction in which the stored data of each ferroelectric memory cell is not inverted, during a disturbance prevention mode performed after the operation mode is performed at least once. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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11. A driving circuit connected to a ferroelectric storage section provided with a plurality of ferroelectric memory cells formed at the intersections of a plurality of word lines and a plurality of bit lines, characterized by comprising:
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a word-line driver for driving the plurality of word lines; and
a plurality of bit-line drivers for driving the plurality of bit lines, and characterized in that the word-line driver and the bit-line drivers apply an operation mode of one of data reading, data re-writing, and data writing to at least one selected cell among the plurality of ferroelectric memory cells, formed at the intersections of the plurality of word lines and the plurality of bit lines, and-apply a voltage to each of the plurality of ferroelectric memory cells in an electric-field direction in which the stored data of each ferroelectric memory cell is not inverted, during a disturbance prevention mode performed after the operation mode is performed at least once.
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Specification