Apparatus and method for input clock signal detection in an asynchronous transfer mode interface unit
First Claim
1. In a data processing system transferring data cells between processing units using an asynchronous transfer mode Utopia protocol, an interface unit comprising:
- apparatus for transferring data cells between the processing units, the transfer of data cells being controlled by an external clock signal; and
a clock detection unit for detecting the absence of the external clock signal, the clock detection unit generating a interface reset signal when the external clock signal is not detected.
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Abstract
In a data processing system have a master-state data processing unit and at least one slave-state data processing unit, the data processing units can be provided with an asynchronous transfer mode interface unit for transferring data cells there between. The interface unit provides and receives signals formatted in the Utopia protocol. The interface unit clock signals from an external source or from the master processing unit. To insure the integrity of the data transfer through the interface unit, a clock signal detection system is provided. When the applied clock signal is not detected, a reset signal and an interrupt signal are generated.
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Citations
15 Claims
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1. In a data processing system transferring data cells between processing units using an asynchronous transfer mode Utopia protocol, an interface unit comprising:
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apparatus for transferring data cells between the processing units, the transfer of data cells being controlled by an external clock signal; and
a clock detection unit for detecting the absence of the external clock signal, the clock detection unit generating a interface reset signal when the external clock signal is not detected. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of insuring the accurate transmission of data through an interface unit acting in an asynchronous transfer mode, the interface unit having an external clock signal applied thereto, the method comprising:
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determining when the external clock signal is present; and
when the external clock signal is not present, generating at least one control signal. - View Dependent Claims (9, 10, 11)
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12. An asynchronous transfer mode Utopia interface unit for providing a interface between an external data processing unit and a direct memory access unit, the interface unit comprising:
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an input buffer memory unit, the input buffer memory unit providing data cells to the direct memory interface unit;
an interface input unit, the interface input unit controlling the transmission of data cells from the external processing system to the input buffer memory unit;
an output buffer memory unit, the output buffer memory unit receiving data cells from the direct memory access unit;
an interface output unit, the interface output unit controlling transmission of data cells from the output buffer memory unit to the external processing system; and
a clock detection unit, the clock detection unit generating a least one control signal when the external clock signal is not present. - View Dependent Claims (13, 14, 15)
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Specification