Processor virtualization mechanism via an enhanced restoration of hard architected states

• US 20040111548A1
• Filed: 12/05/2002
• Published: 06/10/2004
• Est. Priority Date: 12/05/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Starke, William John, Arimilli, Ravi Kumar, Guthrie, Guy Lynn, Cargnoni, Robert Alan
• Granted Patent: US 6,981,083 B2
• Time in Patent Office: Days
• US Class Current: 710/260
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

Claims

1. A method of operating a processor, said method comprising:

storing in a first set of storage locations in the processor a first hard architected state of a first process currently undergoing execution by the processor;

storing in a second set of storage locations in the processor a second hard architected state of a second process that is idle;

in response to receiving a process interrupt at the processor, loading the second hard architected state from the second set of storage locations into the first set of storage locations; and

executing the second process.

2. The method of claim 1, further comprising dynamically replacing the second hard architected state with a third architected state of another idle process while the first process is executing.

3. The method of claim 1, further comprising:

selecting the second process, from a pool of idle processes, for storage of the second hard architected state into the processor, based on a priority of said second process.

4. The method of claim 1, further comprising:

saving the first hard architected state in response to receiving the process interrupt.

5. The method of claim 1, further comprising:

storing a shadow copy of the first hard architected state within the processor; and

in response to receiving the process interrupt in the processor, storing the shadow copy of the first hard architected state in a memory.

6. A processor comprising:

at least one execution unit;

an instruction sequencing unit coupled to the at least one execution unit;

a first set of storage locations for storing a first hard architected state of a first process currently undergoing execution by the processor; and

a second set of storage locations for storing a second hard architected state of a second process that is idle, wherein the second process is from a pool of idle processes, and wherein the second hard architected state that is stored in the second set of storage locations is selected based on a priority assignment of the processing in the pool of idle processes.

7. The processor of claim 6, further comprising means for updating the second hard architected state in response to a process interrupt.

8. The processor of claim 6, further comprising:

execution circuitry for executing memory access instructions, whereby the processor is capable of storing the second architected state independently of execution of memory access instructions by the execution circuitry.

9. The processor of claim 6, further comprising:

a corresponding shadow register coupled to the first set of storage locations, the shadow register containing a shadow copy of at least a portion of the first hard architected state; and

a memory coupled to the shadow register, wherein the processor, in receipt of a process interrupt, stores the shadow copy of the first hard architected state to the memory.

10. A data processing system comprising:

a plurality of processors including a processor in accordance with claim 6;

a volatile memory hierarchy coupled to the plurality of processors; and

an interconnect coupling the plurality of processors.

11. A processor comprising:

means for storing in a first set of storage location in the processor a first hard architected state of a first process currently undergoing execution by the processor;

means for storing in a second set of storage locations in the processor a second hard architected state of a second process that is idle;

means, responsive to receiving a process interrupt at the processor, for loading the second hard architected state from the second set of storage locations into the first set of storage locations; and

means for executing the second process.

12. The processor of claim 11, further comprising means for dynamically replacing the second hard architected state with a third architected state of another idle process while the first process is executing.

13. The processor of claim 11, further comprising:

means for selecting the second process, from a pool of idle processes, for storage in the processor, based on a priority of said second process.

14. The processor of claim 11, further comprising:

means for saving the first hard architected state in response to receiving the process interrupt.

15. The processor of claim 11, further comprising:

means for storing a shadow copy of the first hard architected state within the processor; and

means, responsive to receiving the process interrupt in the processor, for storing the shadow copy of the first hard architected state in a memory.