Processor virtualization mechanism via an enhanced restoration of hard architected states
First Claim
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1. A method of operating a processor, said method comprising:
- storing in a first set of storage locations in the processor a first hard architected state of a first process currently undergoing execution by the processor;
storing in a second set of storage locations in the processor a second hard architected state of a second process that is idle;
in response to receiving a process interrupt at the processor, loading the second hard architected state from the second set of storage locations into the first set of storage locations; and
executing the second process.
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Abstract
A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.
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Citations
15 Claims
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1. A method of operating a processor, said method comprising:
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storing in a first set of storage locations in the processor a first hard architected state of a first process currently undergoing execution by the processor;
storing in a second set of storage locations in the processor a second hard architected state of a second process that is idle;
in response to receiving a process interrupt at the processor, loading the second hard architected state from the second set of storage locations into the first set of storage locations; and
executing the second process. - View Dependent Claims (2, 3, 4, 5)
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6. A processor comprising:
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at least one execution unit;
an instruction sequencing unit coupled to the at least one execution unit;
a first set of storage locations for storing a first hard architected state of a first process currently undergoing execution by the processor; and
a second set of storage locations for storing a second hard architected state of a second process that is idle, wherein the second process is from a pool of idle processes, and wherein the second hard architected state that is stored in the second set of storage locations is selected based on a priority assignment of the processing in the pool of idle processes. - View Dependent Claims (7, 8, 9, 10)
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11. A processor comprising:
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means for storing in a first set of storage location in the processor a first hard architected state of a first process currently undergoing execution by the processor;
means for storing in a second set of storage locations in the processor a second hard architected state of a second process that is idle;
means, responsive to receiving a process interrupt at the processor, for loading the second hard architected state from the second set of storage locations into the first set of storage locations; and
means for executing the second process. - View Dependent Claims (12, 13, 14, 15)
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Specification