Semiconductor device having a lattice-mismatched semiconductor layer on a substrate

• US 20040113143A1
• Filed: 10/03/2003
• Published: 06/17/2004
• Est. Priority Date: 10/07/2002
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fujimoto, Hidetoshi
• Application Number:
  US10/677,224
• Publication Number:
  US 20040113143A1
• Time in Patent Office: Days
• US Class Current: 257/22
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material

Abstract

An indium arsenide (InAs) layer is disposed on a gallium arsenide (GaAs) substrate. A semiconductor layer is disposed over the indium arsenide layer. The semiconductor layer has a lattice constant larger than that of the gallium arsenide substrate and smaller than that of the indium arsenide layer.

Claims

1. A semiconductor device comprising:

a gallium arsenide substrate;

an indium arsenide layer disposed on the gallium arsenide substrate;

a semiconductor layer disposed over the indium arsenide layer and having a lattice constant larger than that of the gallium arsenide substrate and smaller than that of the indium arsenide layer; and

a semiconductor section disposed on the semiconductor layer, lattice-matching with the semiconductor layer and configured as a transistor.

2. The semiconductor device as claimed in claim 1, wherein the semiconductor layer is an indium gallium phosphide layer.

3. The semiconductor device as claimed in claim 1, wherein the semiconductor layer is an indium phosphide layer.

4. A wafer comprising:

a gallium arsenide substrate;

an indium arsenide layer disposed on the gallium arsenide substrate; and

a semiconductor layer disposed over the indium arsenide layer and having a lattice constant larger than that of the gallium arsenide substrate and smaller than that of the indium arsenide layer.

5. The wafer as claimed in claim 4, wherein the semiconductor layer is an indium gallium phosphide layer.

6. The wafer as claimed in claim 4, wherein the semiconductor layer is an indium phosphide layer.

7. A wafer comprising:

a silicon substrate;

a gallium arsenide layer disposed over the silicon substrate;

an indium arsenide layer disposed on the gallium arsenide layer; and

a semiconductor layer disposed over the indium arsenide layer and having a lattice constant larger than that of the gallium arsenide layer and smaller than that of the indium arsenide layer.

8. The wafer as claimed in claim 7, wherein the semiconductor layer is an indium gallium phosphide layer.

9. The wafer as claimed in claim 7, wherein the semiconductor layer is an indium phosphide layer.

10. A method of making a wafer comprising:

forming an indium arsenide layer on a gallium arsenide substrate at a first substrate temperature;

forming a first semiconductor layer having a first lattice constant larger than that of the gallium arsenide substrate and smaller than that of the indium arsenide layer on the indium arsenide layer at the first substrate temperature; and

forming a second semiconductor layer having a second lattice constant larger than that of the gallium arsenide substrate and smaller than that of the indium arsenide layer on the first semiconductor layer at a second substrate temperature higher than the first substrate temperature.

11. The method of making a wafer as claimed in claim 10, wherein the first semiconductor layer is an indium gallium phosphide layer or an indium phosphide layer.

12. The method of making a wafer as claimed in claim 10, wherein the second semiconductor layer is an indium gallium phosphide layer or an indium phosphide layer.

13. A method of making a semiconductor device comprising:

forming an indium arsenide layer on a gallium arsenide substrate at a first substrate temperature;

forming a first semiconductor layer having a first lattice constant larger than that of the gallium arsenide substrate and smaller than that of the indium arsenide layer on the indium arsenide layer at the first substrate temperature;

forming a second semiconductor layer having a second lattice constant larger than that of the gallium arsenide substrate and smaller than that of the indium arsenide layer on the first semiconductor layer at a second substrate temperature higher than the first substrate temperature; and

forming a semiconductor section on the second semiconductor layer lattice-matching with the second semiconductor layer and configured as a transistor.

14. A method of making a semiconductor layer comprising:

forming an indium arsenide layer on a gallium arsenide substrate at a first substrate temperature;

forming a first semiconductor layer having a first lattice constant larger than that of the gallium arsenide substrate and smaller than that of the indium arsenide layer on the indium arsenide layer at the first substrate temperature; and

forming a second semiconductor layer having a second lattice constant larger than that of the gallium arsenide substrate and smaller than that of the indium arsenide layer on the first semiconductor layer at a second substrate temperature higher than the first substrate temperature.