Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses
First Claim
1. A gate structure for a semiconductor device, said semiconductor device having a drain region, a well region and a source region, said gate structure comprising:
- a shielding electrode, respective portions of said shielding electrode being disposed in a common plane with said drain region and said well region, a first dielectric layer disposed between said shielding electrode and said drain and well regions;
a switching electrode, respective portions of said switching electrode being disposed in a common plane with said well region and said source region, a second dielectric layer disposed between said switching electrode and said well and source regions; and
a third dielectric layer disposed between said shielding electrode and said switching electrode.
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Abstract
A gate structure for a semiconductor device includes a shielding electrode and a switching electrode. Respective portions of the shielding electrode are disposed above said drain region and said well region. A first dielectric layer is disposed between the shielding electrode and the drain and well regions. The switching electrode includes respective portions that are disposed above said well region and said source region. A second dielectric layer is disposed between the switching electrode and the well and source regions. A third dielectric layer is disposed between the shielding electrode and the switching electrode.
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Citations
23 Claims
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1. A gate structure for a semiconductor device, said semiconductor device having a drain region, a well region and a source region, said gate structure comprising:
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a shielding electrode, respective portions of said shielding electrode being disposed in a common plane with said drain region and said well region, a first dielectric layer disposed between said shielding electrode and said drain and well regions;
a switching electrode, respective portions of said switching electrode being disposed in a common plane with said well region and said source region, a second dielectric layer disposed between said switching electrode and said well and source regions; and
a third dielectric layer disposed between said shielding electrode and said switching electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device having a substrate, said semiconductor device comprising:
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a well region having a first conductivity type disposed on said substrate;
a source region defined within said well region, said source region having a second conductivity type;
a drain region disposed adjacent to said well region, said drain region having said second conductivity type;
a gate structure including a shielding electrode and a switching electrode, respective portions of said shielding electrode being disposed in a common plane with said drain region and said well region, a first dielectric layer disposed between said shielding electrode and said drain and well regions, respective portions of said switching electrode being disposed in a common plane with said well region and said source region, a second dielectric layer disposed between said switching electrode and said well and source regions, a third dielectric layer disposed between said shielding electrode and said switching electrode. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A process for fabricating a semiconductor device, comprising:
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etching a trench in a well region of the semiconductor, said trench being adjacent a source region of the semiconductor;
lining walls and a bottom of the trench with a first dielectric layer;
depositing a first conductive layer of material;
etching the first conductive layer of material to thereby form a shielding electrode;
etching the first dielectric layer;
depositing a second layer dielectric layer over the shielding electrode and over the walls of the trench; and
depositing a switching electrode onto said second dielectric layer within said trench.
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Specification