×

Power metal oxide semiconductor field effect transistor layout

  • US 20040113205A1
  • Filed: 09/22/2003
  • Published: 06/17/2004
  • Est. Priority Date: 11/07/2002
  • Status: Active Grant
First Claim
Patent Images

1. A power metal oxide semiconductor field effect transistor (MOSFET) layout comprising:

  • a substrate;

    a plurality of cells, each of said cells including;

    a base portion;

    a plurality of protruding portions extending from the base portion, each of said cells being geometrically configured with the base portion and the plurality of protruding portions defining a closed cell boundary enclosing each of said cells; and

    a plurality of photo-resist regions;

    wherein the cells are formed over the substrate, and the closed cell boundaries of the cells are arranged regularly with each other with no overlapping among the cells;

    wherein the base portions are disposed in a matrix arrangement having rows and columns, the base portions being oriented from end to end in a direction of the columns and the protruding portions extending from the base portions along a direction of the rows;

    wherein the photo-resist regions cover the base portions on the same column; and

    wherein none of the protruding portions are disposed between the base portions on the same column; and

    wherein the cells are doped with N type dopants by using the photo-resist regions as masks.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×