Vertical MOSFET SRAM cell

• US 20040113207A1
• Filed: 12/11/2002
• Published: 06/17/2004
• Est. Priority Date: 12/11/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis L., Radens, Carl J., Mandelman, Jack A., Gluschenkov, Oleg
• Granted Patent: US 7,138,685 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.

Claims

1. A method of forming a vertical Static Random Access Memory (SRAM) cell device comprising the steps as follows:

forming pass gate FET transistors,

forming a pair of vertical pull-down FET transistors with a first common body and a first common source region,

forming a pair of vertical pull-up FET transistors with a second common body and a second common source region, and

connecting the FET transistors in an SRAM cell circuit.

2. The method of claim 1 including the steps as follows:

forming a common diffusion for the uppermost diffusion of an FET and then etching the diffusion to form a recess thereby forming isolated diffusions above a common body.

3. The method of claim 1 including the steps as follows:

forming a common diffusion for the uppermost diffusion of an FET,

etching the common diffusion to form a recess above each of the first common body and the second common body thereby forming isolated diffusions above each of the first common body and the second common body and

filling each recess with a dielectric material.

4. The method of claim 1 including the steps of:

forming the pull-up FET transistors with first common source, a first common body and a first common drain and then bisecting the first common drain with a first dielectric isolation region

forming the pull-down FET transistors with a second common source, a second common body and a second common drain regions and then bisecting the second common drain with a second dielectric isolation region.

5. The method of claim 1 wherein the pass gate FET transistors are selected from the group consisting of planar and vertical transistors.

6. The method in claim 1 where the SRAM device includes dual pairs of pass gate FET transistors forming a dual-port SRAM cell.

7. The method of claim 1 including the step of connecting the FET transistors with a sublithographic borderless contact structure formed between the upper diffusion area of non-planar transistor and a zero (M0) metallization layer.

8. The method in claim 1 including the step of connecting the FET transistors with a sublithographic borderless contact structure formed between the gate electrode of non-planar transistor and a zero (M0) metallization layer.

9. The method in claim 1 including the step of connecting the FET transistors with a sublithographic borderless contact structure formed between the gate electrode of a non-planar transistor and a second metallization layer.

10. The method in claim 1 wherein common gate electrodes interconnect pull-down and pull-up vertical FETs.

11. The method in claim 1 wherein the gate electrode is made of a heavily doped polycrystalline semiconductor material selected from the group consisting of Si, SiGe, SiGeC

12. The method of claim 1 wherein the device is a silicon on insulation device formed by the steps as follows:

forming a silicon layer on a planar insulator,

patterning the silicon layer into parallel islands,

forming a pull-up island with doped vertical pull-up strata in a first one of the parallel island comprising an upper pull-up stratum, a pull-up body stratum and a pull-up lower stratum, the upper pull-up stratum and the pull-up lower stratum having opposite types of dopant from the pull-up body stratum,

forming a pull-down island with doped vertical pull-down strata in a second one of the parallel islands comprising an upper pull-down stratum, a pull-down body stratum and a pull-down lower stratum, the upper pull-down stratum and the pull-down lower stratum having opposite types of dopant from the pull-down body stratum,

etching to form a pull-down isolation space bisecting the upper pull-down stratum to form pull-down drain regions of the pair of vertical pull-down FET transistors, with the pull-down isolation space reaching down to the pull-down body stratum;

etching to form a pull-up isolation space bisecting the upper pull-up stratum to form pull-up drain regions of the pair of vertical pull-up FET transistors, with the pull-up isolation space reaching down to the pull-up body stratum,

filling the pull-down isolation space and the pull-up isolation space with an isolation dielectric.

13. The method of claim 12 including the steps as follows:

forming a common diffusion for the uppermost diffusion of an FET and then etching the diffusion to form a recess thereby forming isolated diffusions above a common body.

14. The method of claim 12 including the steps as follows:

forming a common diffusion for the uppermost diffusion of an FET,

etching the common diffusion to form a recess above each of the first common body and the second common body thereby forming isolated diffusions above each of the first common body and the second common body and

filling each recess with a dielectric material

15. The method in claim 12 wherein common gate electrodes interconnect pull-down and pull-up vertical FETs.

16. The method in claim 12 wherein the gate electrode is made of a heavily doped polycrystalline semiconductor material selected from the group consisting of Si, SiGe, SiGeC

17. The method in claim 12 wherein the gate electrode is made entirely or partially of metallic conductor

18. The method in claim 12 wherein the gate electrode completely or partially surrounds the transistor body

19. The method in claim 12 wherein common gate electrodes interconnect pull-down and pull-up vertical

20. A vertical Static Random Access Memory (SRAM) cell device comprising the steps as follows:

a pair of pass gate vertical FET transistors,

a pair of vertical pull-down FET transistors with a first common body and a first common source,

a pair of vertical pull-up FET transistors with a second common body and a second common source, and

the FET transistors connected in an SRAM cell circuit.