Stress inducing spacers

• US 20040113217A1
• Filed: 12/12/2002
• Published: 06/17/2004
• Est. Priority Date: 12/12/2002
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Doris, Bruce B., Dokumaci, Omer H., Mandelman, Jack A., Baie, Xavier
• Granted Patent: US 6,825,529 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

Claims

1. A spacer structure for devices formed in a substrate, the devices each having a channel for conducting charge in a longitudinal direction and each having a gate terminal adjacent the channel, the structure comprising:

a first spacer structure for a first one of the devices, the first spacer structure comprising a first stress inducing material adjacent to both a sidewall of the first one of the device'"'"'s gate terminal and its channel which applies a first type of mechanical stress on the first one of the devices at least in the longitudinal direction; and

a second spacer structure for a second one of the devices, the second spacer structure comprising a second stress inducing material adjacent to both a sidewall of the second one of the device'"'"'s gate terminal and its channel which applies a second type of mechanical stress on the second one of the devices at least in the longitudinal direction.

2. The spacer structure of claim 1, wherein the first one of the devices is an

NFET and the second one of the devices is a PFET.

3. The spacer structure of claim 2, wherein the first stress inducing material is TEOS and the second stress inducing material is HDP.

4. The spacer structure of claim 2, wherein the first stress inducing material is a tensile deposited nitride and the second stress inducing material is a compressive deposited nitride.

5. A method for making devices in a substrate, the devices each having a gate terminal on the substrate and each extending in the substrate in a longitudinal direction, the method comprising:

disposing a first spacer material on the sidewalls of the gate terminal and on a top surface of the substrate of a first one of the devices to apply a first type of mechanical stress on the first one of the devices in the longitudinal direction; and

disposing a second spacer material on the sidewalls of the gate terminal and on the top surface of the substrate of a second one of the devices to apply a second type of mechanical stress on the second one of the devices in the longitudinal direction.

6. The method of claim 5 wherein the steps of disposing the first and second spacer material includes the steps of:

covering the gate terminal of the first one of the devices with the first spacer material; and

covering the gate terminal of the second one of the devices with the second spacer material.

7. The method of claim 6, wherein the steps of covering the gate terminals of the first and second ones of the devices further includes the steps of:

initially covering both the first and second ones of the gate terminals with the first spacer material; and

blocking the first one of the devices with a block mask while removing the first spacer material from the second one of the devices.

8. The method of claim 7, further comprising the steps of:

covering both the first and second ones of the gate terminals with the second spacer material; and

blocking the second one of the devices with a block mask while removing the second spacer material from the first one of the devices.

9. The method of claim 8, further comprising the step of:

etching the devices to remove the first and second spacer materials from a top surface of the gate terminals of the first and second ones of the devices, respectively.

10. The method of claim 5, wherein the step of disposing a first spacer material comprises the step of:

disposing TEOS on the sidewalls of the gate terminal of the first one of the devices and on the top surface of the substrate.

11. The method of claim 5, wherein the step of disposing a second spacer material comprises the step of:

disposing HDP on the sidewalls of the gate terminal of the second one of the devices and on the top surface of the substrate.

12. The method of claim 5, wherein the step of disposing a first spacer material comprises the step of:

disposing tensile nitride on the sidewalls of the gate terminal of the first one of the devices and on the top surface of the substrate.

13. The method of claim 5, wherein the step of disposing a second spacer material comprises the step of:

disposing compressive nitride on the sidewalls of the gate terminal of the second one of the devices and on the top surface of the substrate.

14. An IC chip having formed thereon a plurality of SOI regions, the SOI regions having sides extending in a longitudinal direction and ends extending in a transverse direction, a portion of the SOI regions comprising:

a layer formed on the ends of said portion of the SOI regions which induces a mechanical stress in the longitudinal direction in said portion of the SOI regions.

15. The IC chip of claim 14 wherein the layer formed on the ends of the portion of the SOI regions comprises oxidized silicon which induces a compressive mechanical stress.

16. A method for making a plurality of stressed SOI regions and a plurality of unstressed SOI regions on the same substrate, the stressed SOI regions and the unstressed SOI regions each having sides extending in a longitudinal direction and ends extending in a transverse direction, the method comprising:

depositing a stress inducing layer only on the ends of the stressed SOI regions; and

exposing the stress inducing layer on the ends of the stressed SOI regions to a preselected agent for inducing a longitudinal mechanical stress in the stressed SOI regions.

17. The method of claim 16 wherein the step of exposing includes exposing the stress inducing layer to oxygen for expanding the stress inducing layer and for inducing a compressive longitudinal stress in the stressed SOI regions.

18. The method of claim 16 further comprising:

etching through an SOI layer on the substrate for defining both the stressed and unstressed SOI regions on the substrate; and

covering the stressed and unstressed SOI regions with the stress inducing layer.

19. The method of claim 18 further comprising:

forming a resist layer on a portion of the stress inducing layer that covers the stressed SOI regions.

20. The method of claim 19 further comprising:

removing the stress inducing layer covering the unstressed SOI regions using the resist layer as a mask.