Semiconductor device and process for fabricating the same

• US 20040113245A1
• Filed: 11/21/2003
• Published: 06/17/2004
• Est. Priority Date: 03/24/2000
• Status: Active Grant

• Current Assignee: Masaki Hatano, Teruo Hirayama, Yuji Takaoka, Yukihiro Kamide
• Original Assignee: Masaki Hatano, Teruo Hirayama, Yuji Takaoka, Yukihiro Kamide
• Inventors: Hatano, Masaki, Takaoka, Yuji, Hirayama, Teruo, Kamide, Yukihiro
• Granted Patent: US 7,135,378 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A semiconductor device of MCM type allowing high-density assembly and a process of fabricating the same is provided.

There are provided semiconductor chips mounted on a supporting substrate and incrusted in an insulation film on the supporting substrate and wiring formed in the insulation film so as to connect to each semiconductor chip through connection holes provided in the insulation film. Then, an interlayer dielectric covers such wiring that is connected to an upper layer wiring, through connection holes provided in such interlayer dielectric.

In addition, an upper layer insulation film covers the upper layer wiring, and an electrode, connected to such upper layer wiring through another connection hole, is provided on such upper layer insulation film.

Claims

1. A semiconductor device, comprising:

a plurality of semiconductor chips mounted on a substrate;

an insulation film provided on said substrate, wherein said plurality of semiconductor chips are incrusted in said insulation film; and

wiring provided on said insulation film, wherein said wiring is connected to said plurality of semiconductor chips through a connection hole formed on said insulation film.

2. The semiconductor device according to claim 1, further comprising

an upper layer insulation film provided on said insulation film, wherein said upper layer insulation film covers said wiring;

and

an electrode provided on said upper layer insulation film, wherein said electrode is connected to said wiring through a connection hole formed on said upper layer insulation film.

3. The semiconductor device according to claim 1, wherein

said wiring is arranged so that a circuit included in a semiconductor chip among said plurality of semiconductor chips is a shared circuit, shared with another semiconductor chip of said plurality of semiconductor chips.

4. The semiconductor device according to claim 3, wherein

said shared circuit is an input-output interface circuit for an external equipment.

5. The semiconductor device according to claim 3, wherein said shared circuit is a power supply circuit.

6. The semiconductor device according to claim 3, wherein said shared circuit is an electrostatic protection circuit.

7. A semiconductor device, comprising:

a plurality of semiconductor chips;

an insulation layer supporting said plurality of semiconductor chips, wherein a surface of said plurality of semiconductor chips is incrusted in said insulation layer and another surface of said plurality of semiconductor chips are exposed; and

wiring provided on said insulation layer, wherein said wiring is connected to each semiconductor chip of said plurality of semiconductor chips through a connection hole formed on said insulation layer.

8. The semiconductor device according to claim 7, further comprising

an upper layer insulation film provided on said insulation layer, wherein said upper layer insulation film covers said wiring;

and

an electrode provided on said upper layer insulation film, wherein said electrode is connected to said wiring through a connection hole formed on said upper layer insulation film.

9. The semiconductor device according to claim 7, wherein

said wiring is arranged so that a circuit included in a semiconductor chip among said plurality of semiconductor chips is a shared circuit, shared with another semiconductor chip of said plurality of semiconductor chips.

10. The semiconductor device according to claim 9, wherein said shared circuit is an input-output interface circuit for an external equipment.

11. The semiconductor device according to claim 9, wherein said shared circuit is a power supply circuit.

12. The semiconductor device according to claim 9, wherein said shared circuit is an electrostatic protection circuit.

13. A semiconductor device, comprising a plurality of semiconductor chips mounted on a substrate, wherein a circuit of a semiconductor chip among said plurality of semiconductor chips is a shared circuit, shared with another semiconductor chip of said plurality of semiconductor chips.

14. The semiconductor device according to claim 13, wherein said shared circuit is an input-output interface circuit for an external equipment.

15. The semiconductor device according to claim 13, wherein said shared circuit is a power supply circuit.

16. The semiconductor device according to claim 13, wherein said shared circuit is an electrostatic protection circuit.

17. A method of fabrication of a semiconductor device, comprising the steps of:

die bonding of a plurality of semiconductor chips on a substrate;

forming of an insulation film on said substrate, wherein said plurality of semiconductor chips is incrusted in said insulation film;

forming of a connection hole reaching a semiconductor chip of said plurality of semiconductor chips on said insulation film; and

forming of wiring on said insulation film, wherein said wiring is connected to said semiconductor chip through said connection hole.

18. The method of fabrication of a semiconductor device according to claim 17, further comprising the steps of:

forming of an upper layer insulation film on said insulation film, wherein said upper layer insulation film covers said wiring;

forming of a connection hole reaching said wiring, on said upper layer insulation film; and

forming of an electrode on said upper layer insulation film, wherein said electrode is connected to said wiring through said connection hole.

19. The method of fabrication of a semiconductor device according to claim 17, wherein said substrate is a semiconductor wafer.

20. The method of fabrication of a semiconductor device according to claim 17, wherein

said die bonding of said plurality of semiconductor chips on said substrate comprises die bonding of each said semiconductor chip on said substrate, wherein each said semiconductor chip is set so as to float on an adhesive resin applied on said substrate.

21. The method of fabrication of a semiconductor device according to claim 17, wherein

after said step of forming said wiring, said substrate is removed from said semiconductor chip and said insulation film.