Method and apparatus for reducing electrical interconnection fatigue

• US 20040113285A1
• Filed: 12/17/2002
• Published: 06/17/2004
• Est. Priority Date: 12/17/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Tay, Cheng Siew, Cheng, Swee Kian, Goh, Eng Huat
• Granted Patent: US 7,173,342 B2
• Time in Patent Office: Days
• US Class Current: 257/786
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 2201/09418 Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
• CPC Class Codes: H05K 2201/0989 Coating free areas, e.g. areas other than pads or lands free of solder resist
• CPC Class Codes: H05K 2201/099 Coating over pads, e.g. solder resist partly over pads
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/3452 Solder masks

Abstract

A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.

Claims

1. A substrate, comprising:

an array having a plurality electrical interconnects on a surface of the substrate, the array having an outer portion and a center; and

a dielectric layer, wherein the dielectric layer covers a portion of the substrate and contacts at least a portion of each of the plurality of electrical interconnects to define a dielectric electrical interconnect edge portion and a non-dielectric electrical interconnect edge portion on each of the plurality of electrical interconnects, the non-dielectric electrical edge portion being oriented on the surface to resist crack propagation.

2. The substrate of claim 1, wherein the non-dielectric electrical interconnect edge portion is oriented distal to the center to resist inward crack propagation.

3. The substrate of claim 1, wherein the non-dielectric electrical interconnect edge portion is oriented proximal to the center to resist outward crack propagation.

4. The substrate of claim 1, wherein the ratio of the dielectric defined edge portion to the non-dielectric defined edge portion is greater than one.

5. The substrate of claim 1, wherein the ratio of the dielectric defined edge portion to the non-dielectric defined edge portion is less than one.

6. The substrate of claim 1, further comprising a corresponding via and a corresponding linking interconnect for each electrical interconnect, the electrical interconnect being spaced apart from the corresponding via a predetermined distance, the corresponding linking interconnect electrically interconnecting the electrical interconnect to the corresponding via.

7. The substrate of claim 6, wherein the corresponding via is oriented between the electrical interconnect and the center of the array.

8. The substrate of claim 6, wherein the electrical interconnect is oriented between the corresponding via and the center of the array.

9. An electronic assembly, comprising:

a system substrate;

a microelectronic package electrically interconnected with the system substrate, the microelectronic package further comprising;

a microelectronic die; and

a substrate, the substrate further comprising an array having a plurality electrical interconnects on a surface of the substrate, the array having an outer portion and a center, and a dielectric layer, wherein the dielectric layer covers a portion of the substrate and contacts at least a portion of each the plurality of electrical interconnects, to define a dielectric electrical interconnect edge portion and a non-dielectric electrical interconnect edge portion on each of the plurality of electrical interconnects, the non-dielectric electrical edge portion being oriented on the surface to resist crack propagation.

10. The substrate of claim 9, wherein the non-dielectric electrical interconnect edge portion is oriented distal to the center to resist inward crack propagation.

11. The substrate of claim 9, wherein the non-dielectric electrical interconnect edge portion is oriented proximal to the center to resist outward crack propagation.

12. The substrate of claim 9, wherein the ratio of the dielectric defined edge portion to the non-dielectric defined edge portion is greater than one.

13. The substrate of claim 9, wherein the ratio of the dielectric defined edge portion to the non-dielectric defined edge portion is less than one.

14. The substrate of claim 9, further comprising a corresponding via and a corresponding linking interconnect for each electrical interconnect, the electrical interconnect being spaced apart from the corresponding via a predetermined distance, the corresponding linking interconnect electrically interconnecting the electrical interconnect to the corresponding via.

15. The substrate of claim 14, wherein the corresponding via is oriented between the electrical interconnect and the center of the array.

16. The substrate of claim 14, wherein the electrical interconnect is oriented between the corresponding via and the center of the array.

17. An electronic assembly, comprising:

a microelectronic package; and

a system substrate electrically interconnected with the microelectronic package, the system substrate further comprising an array having a plurality electrical interconnects on a surface of the substrate, the array having an outer portion and a center, and a dielectric layer, wherein the dielectric layer covers a portion of the substrate and contacts at least a portion of each of the plurality of electrical interconnects to define a dielectric electrical interconnect edge portion and a non-dielectric electrical interconnect edge portion on each of the plurality of electrical interconnects, the non-dielectric electrical edge portion being oriented on the surface to resist crack propagation.

18. The substrate of claim 17, wherein the non-dielectric electrical interconnect edge portion is oriented distal to the center to resist inward crack propagation.

19. The substrate of claim 17, wherein the non-dielectric electrical interconnect edge portion is oriented proximal to the center to resist outward crack propagation.

20. The substrate of claim 17, wherein the ratio of the dielectric defined edge portion to the non-dielectric defined edge portion is greater than one.

21. The substrate of claim 17, wherein the ratio of the dielectric defined edge portion to the non-dielectric defined edge portion is less than one.

22. The substrate of claim 17, further comprising a corresponding via and a corresponding linking interconnect for each electrical interconnect, the electrical interconnect being spaced apart from the corresponding via a predetermined distance, the corresponding linking interconnect electrically interconnecting the electrical interconnect to the corresponding via.

23. The substrate of claim 22, wherein the corresponding via is oriented between the electrical interconnect and the center of the array.

24. The substrate of claim 22, wherein the electrical interconnect is oriented between the corresponding via and the center of the array.

25. A method for interconnecting electrical components, comprising:

providing a substrate having an array having a plurality electrical interconnects on a surface of the substrate, the array having an outer portion and a center, a dielectric layer, wherein the dielectric layer covers a portion of the substrate and contacts at least a portion of each of the plurality of electrical interconnects to define a dielectric electrical interconnect edge portion and a non-dielectric electrical interconnect edge portion on each of the plurality of electrical interconnects;

identifying a potential crack initiation point; and

orienting the non-dielectric defined edge portion of each electrical interconnect at the potential crack initiation point.

26. The method of claim 25, further comprising:

orienting the dielectric defined edge portion of each of the plurality of electrical interconnects proximal to the center of the array.

27. The method of claim 25, further comprising:

orienting the dielectric defined edge portion of each one of the plurality of electrical interconnect distal to the center of the array.

28. The method of claim 25, further comprising:

electrically interconnecting the each of the plurality of electrical interconnects to a corresponding one of a plurality of vias by a linking interconnect; and

orienting the at least one via between the corresponding electrical interconnect and the center of the array.

29. The method of claim 25, further comprising:

electrically interconnecting the each of the plurality of electrical interconnects to a corresponding one of a plurality of vias by a linking interconnect; and

orienting each electrical interconnect between the corresponding via and the center of the array.