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Partial reconfiguration of a programmable logic device using an on-chip processor

  • US 20040113655A1
  • Filed: 12/13/2002
  • Published: 06/17/2004
  • Est. Priority Date: 12/13/2002
  • Status: Active Grant
First Claim
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1. A programmable logic device comprising:

  • a configuration memory array having a plurality of frames, wherein the configuration memory array stores configuration data values for controlling the configuration of the programmable logic device;

    a processor configured to implement a partial reconfiguration of the programmable logic device by reading a frame from the configuration memory array, modifying only a select subset of the frame, thereby creating a modified frame, and writing the modified frame back to the configuration memory array.

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