Signal amplifier using a doherty amplifier

• US 20040113698A1
• Filed: 07/15/2003
• Published: 06/17/2004
• Est. Priority Date: 11/18/2002
• Status: Abandoned Application

• Current Assignee: Postech Foundation
• Original Assignee: Postech Foundation
• Inventors: Yang, Youngoo, Kim, Bumman
• Application Number:
  US10/618,772
• Publication Number:
  US 20040113698A1
• Time in Patent Office: Days
• US Class Current: 330/295
• CPC Class Codes: H03F 1/0288 using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
• CPC Class Codes: H03F 3/602 Combinations of several amplifiers

Abstract

A signal amplifier includes a splitter for splitting an input signal into first and second signals, first and second bias control networks for generating a base bias signal for a Doherty amplifier in accordance with a power level of the input signal, a carrier amplifier for amplifying the first input signal, a peaking amplifier for amplifying the second input signal and a Doherty output network for combining the amplified signals. Through a simplified transformation of characteristic impedances in the Doherty output network, minimization of circuitry including the signal amplifier is obtained. Further, by controlling the Doherty amplifier in accordance with the power level of the input signal, both high efficiency and high linearity of the signal amplifier are achieved.

Claims

1. A signal amplifier comprising:

a splitter for splitting an input signal into two signals to be transmitted respectively through a first and a second transmission paths;

a first and a second bias control networks for generating base bias signals corresponding to a power level of the input signal by alternating their operation modes, wherein the power level of the input signal lower than a predetermined threshold level is associated with a low input power drive mode and the power level of the input signal higher than the predetermined threshold level is associated with a high input power drive mode of the control networks;

a Doherty amplifier including a carrier amplifier for amplifying the signal transmitted through the first transmission path and a peaking amplifier for amplifying the signal transmitted through the second transmission path; and

a Doherty output network for matching and outputting the signals amplified at the carrier amplifier and the peaking amplifier.

2. The signal amplifier of claim 1, wherein the carrier amplifier reduces idle current in the low input power drive mode and functions as a class AB amplifier in the high input power drive mode in accordance with the bias signal transmitted from the first bias control network;

and

the peaking amplifier is turned off in the low input power drive mode and functions as a class AB amplifier in the high input power drive mode in accordance with the bias signal transmitted from the second bias control network.

3. The signal amplifier of claim 1, wherein the first bias control network includes a V_contC pin for receiving different control voltages depending on the power level of the input signal and a V_refC pin for transmitting the different base bias signal to the carrier amplifier in accordance with the control voltage fed to the V_contC pin;

and

the second bias control network includes a V_contP pin for receiving different control voltages depending on the power level of the input signal and a V_refP pin for transmitting the different base bias signal to the peaking amplifier in accordance with the control voltage fed to the V_contP pin.

4. The signal amplifier of claim 3, wherein the control voltages fed to the V_contC pin is equal to that of the V_contP pin.

5. The signal amplifier of claim 4, wherein the V_contC pin and the V_contP pin are fed with about 2˜

3 V in the low input power drive mode and about 0 V in the high input power drive mode.

6. The signal amplifier of claim 1, further comprising an attenuator for compensating a gain difference between the first and the second transmission paths in the high input power drive mode, which is located at one of input ends of the carrier amplifier and the peaking amplifier.

7. The signal amplifier of claim 6, wherein the attenuator is implemented by using passive elements or variable gain amplifiers (VGAs).

8. The signal amplifier of claim 1, further comprising a first transmission line for compensating a delay and a phase differences between the first and the second transmission paths.

9. The signal amplifier of claim 8, wherein the first transmission line is implemented by using lumped elements.

10. The signal amplifier of claim 1, wherein the Doherty output network includes:

a second transmission line having characteristic impedance R_oc and phase Θ

_c, which is arranged at an output end of the carrier amplifier;

a third transmission line having characteristic impedance R_op and phase Θ

_p, which is arranged at an output end of the peaking amplifier; and

a fourth transmission line having characteristic impedance R_oc and phase 90°

, which is coupled with the second transmission line.

12. The signal amplifier of claim 10, wherein the characteristic impedance R_op is adjusted in accordance with the formula of Rop=50·

(1+α

), where α

is a size ratio of the peaking amplifier to the carrier amplifier.

13. The signal amplifier of claim 10, wherein the characteristic impedance R_oc is adjusted in accordance with the formula of

11. The signal amplifier 10, wherein the second, the third and the fourth transmission lines are implemented by using lumped elements.