Thin film transistor array panel for liquid crystal display and method for manufacturing the same

• US 20040114059A1
• Filed: 11/12/2003
• Published: 06/17/2004
• Est. Priority Date: 09/26/2001
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Nam-Hung, Lee, Chang-Hun, Lyu, Jae-Jin, Chang, Hak-Sun
• Granted Patent: US 7,209,192 B2
• Time in Patent Office: Days
• US Class Current: 349/39
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.

Claims

1. A thin film transistor array panel comprising:

an insulating substrate;

a gate line assembly formed on the insulating substrate with gate lines, and gate electrodes;

a gate insulating layer covering the gate line assembly;

a semiconductor pattern formed on the gate insulating layer;

a data line assembly formed on the gate insulating layer overlaid with the semiconductor pattern, the data line assembly having data lines crossing over the gate lines, source electrodes connected to the data lines, and drain electrodes facing the source electrodes;

storage capacitor electrode lines formed between the neighboring data lines while crossing over the gate lines;

a passivation layer covering the data line assembly, the storage capacitor electrode lines and the semiconductor pattern while bearing contact holes exposing the drain electrodes; and

pixel electrodes formed on the passivation layer while being connected to the drain electrodes through the contact holes, the pixel electrodes being overlapped with the storage capacitor electrode lines.

2. The thin film transistor array panel of claim 1 further comprising a common interconnection line commonly interconnecting the storage capacitor electrode lines.

3. The thin film transistor array panel of claim 2 wherein the common interconnection line is formed with the same material as the pixel electrodes while crossing over the data lines in an insulated manner.

4. The thin film transistor array panel of claim 2 wherein the common interconnection line is formed with the same material as the gate lines while crossing over the data lines in an insulated manner.

5. The thin film transistor array panel of claim 3 wherein the passivation layer has a plurality of contact holes exposing the storage capacitor electrode lines, and the common interconnection line is connected to the storage capacitor electrode lines through the contact holes.

6. The thin film transistor array panel of claim 2 further comprising a subsidiary interconnection line connected to the storage capacitor electrode lines.

7. The thin film transistor array panel of claim 6 wherein the storage capacitor electrode lines and the subsidiary interconnection line are formed with the same material.

8. The thin film transistor array panel of claim 1 further comprising:

gate pads formed at one-sided end portions of the gate lines;

data pads formed at one-sided end portions of the data lines;

first contact holes formed at the passivation layer and the gate insulating layer while exposing the gate pads;

second contact holes formed at the passivation layer while exposing the data pads; and

subsidiary gate and data pads connected to the gate and the data pads through the first and the second contact holes.

9. A liquid crystal display comprising:

the thin film transistor array panel of claim 1;

a counter substrate facing the thin film transistor array panel; and

a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel.

10. The liquid crystal display of claim 9 having storage capacitors with an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.

11. The liquid crystal display of claim 10 wherein the electrostatic capacitance of the storage capacitors is greater than the electrostatic capacitance of the liquid crystal layer by 95% or more.

12. The liquid crystal display of claim 9 wherein the thin film transistor array panel further comprises a common interconnection line commonly interconnecting the storage capacitor electrode lines.

13. The liquid crystal display of claim 12 wherein the common interconnection line is formed with the same material as the pixel electrodes while crossing over the data lines in an insulated manner.

14. The liquid crystal display of claim 13 wherein the passivation layer has a plurality of contact holes exposing the storage capacitor electrode lines, and the common interconnection line is connected to the storage capacitor electrode lines through the contact holes.

15. The liquid crystal display of claim 12 wherein the thin film transistor array panel further comprises a subsidiary interconnection line connected to the storage capacitor electrode lines.

16. The liquid crystal display of claim 15 wherein the storage capacitor electrode lines and the subsidiary interconnection line are formed with the same material.

17. A thin film transistor array panel comprising:

an insulating substrate;

a gate line assembly and a storage capacitor line assembly formed on the insulating substrate, the gate line assembly having gate lines and gate electrodes;

a gate insulating layer covering the gate line assembly and the storage capacitor line assembly;

a semiconductor pattern formed on the gate insulating layer;

a data line assembly and storage capacitor conductive patterns formed on the gate insulating layer overlaid with the semiconductor pattern, the data line assembly having data lines, source electrodes and drain electrodes, the storage capacitor conductive patterns being partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors;

a passivation layer covering the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern;

first and second contact holes formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns, respectively; and

pixel electrodes formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes, the pixel electrodes forming second storage capacitors in association with parts of the storage capacitor line assembly.

18. The thin film transistor array panel of claim 17 wherein the storage capacitor line assembly has storage capacitor electrode lines proceeding parallel to the gate lines, and storage capacitor electrode patterns connected to the storage capacitor electrode lines.

19. The thin film transistor array panel of claim 18 wherein the storage capacitor electrode patterns are overlapped with the storage capacitor conductive patterns to thereby form the first storage capacitors, and the storage capacitor electrode lines are overlapped with the pixel electrodes to thereby form the second storage capacitors.

20. The thin film transistor array panel of claim 19 wherein the storage capacitor electrode patterns are formed within pixel regions defined by the gate lines and the data lines.

21. The thin film transistor array panel of claim 19 wherein the storage capacitor electrode patterns are formed with a bar shape along the data lines while being overlapped with peripheral portions of the pixel electrodes.

22. A liquid crystal display comprising:

the thin film transistor array panel of claim 17;

a counter substrate facing the thin film transistor array panel; and

a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel.

23. The liquid crystal display of claim 22 wherein the first and the second storage capacitors have an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.

24. A thin film transistor array panel comprising:

an insulating substrate;

a gate line assembly formed on the insulating substrate, the gate line assembly having first gate lines, gate electrodes connected to the first gate lines, and second gate lines spaced apart from the first gate lines with a predetermined distance;

a gate insulating layer covering the gate line assembly;

a semiconductor pattern formed on the gate insulating layer while being overlapped with the gate electrodes;

a data line assembly and storage capacitor conductive patterns formed on the gate insulating layer overlaid with the semiconductor pattern, the data line assembly having data lines crossing over the first and the second gate lines, source electrodes and drain electrodes, the storage capacitor conductive patterns being partially overlapped with the second gate lines to thereby form first storage capacitors;

a passivation layer covering the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern;

first and second contact holes formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns, respectively; and

pixel electrodes formed at the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes, the pixel electrodes being partially overlapped with the second gate lines to thereby form second storage capacitors.

25. A liquid crystal display comprising:

the thin film transistor array panel of claim 24;

a counter substrate facing the thin film transistor array panel; and

a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel.

26. The liquid crystal display of claim 25 wherein the first and the second storage capacitors have an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.

27. A thin film transistor array panel comprising:

an insulating substrate;

a gate line assembly and storage capacitor electrode lines formed on the insulating substrate, the gate line assembly having gate lines and gate electrodes;

a gate insulating layer covering the gate line assembly and the storage capacitor electrode lines;

first contact holes formed at the gate insulating layer while exposing the storage capacitor electrode lines;

a semiconductor pattern formed on the gate insulating layer while being overlapped with the gate electrodes;

a data line assembly and storage capacitor conductive patterns formed on the gate insulating layer overlaid with the semiconductor pattern, the data line assembly having data lines, source electrodes and drain electrodes, the storage capacitor conductive patterns being connected to the storage capacitor electrode lines through the first contact holes;

a passivation layer covering the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern;

second contact holes formed at the passivation layer while exposing the drain electrodes; and

pixel electrodes formed at the passivation layer while being connected to the drain electrodes through the second contact holes, the pixel electrodes being overlapped with the storage capacitor conductive patterns to thereby form first storage capacitors while being partially overlapped with the storage capacitor electrode lines to thereby form second storage capacitors.

28. The thin film transistor array panel of claim 27 wherein the storage capacitor electrode lines proceed parallel to the gate lines.

29. The thin film transistor array panel of claim 27 wherein the storage capacitor conductive patterns are overlapped with the storage capacitor electrode lines.

30. The thin film transistor array panel of claim 29 wherein the storage capacitor conductive patterns are formed within pixel regions defined by the gate lines and the data lines.

31. The thin film transistor array panel of claim 27 wherein the storage capacitor electrode patterns are formed with a bar shape along the data lines while being overlapped with peripheral portions of the pixel electrodes.

32. A liquid crystal display comprising:

the thin film transistor array panel of claim 27;

a counter substrate facing the thin film transistor array panel; and

a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel.

33. The liquid crystal display of claim 32 wherein the first and the second storage capacitors have an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.

34. A thin film transistor array panel comprising:

an insulating substrate;

a gate line assembly formed on the insulating substrate, the gate line assembly having first gate lines, gate electrodes connected to the first gate lines, and second gate lines spaced apart from the first gate lines with a predetermined distance;

a gate insulating layer covering the gate line assembly;

first contact holes formed at the gate insulating layer while partially exposing the second gate lines;

a semiconductor pattern formed on the gate insulating layer while being overlapped with the gate electrodes;

a data line assembly and storage capacitor conductive patterns formed on the gate insulating layer overlaid with the semiconductor pattern, the data line assembly having data lines crossing over the first and the second gate lines, source electrodes and drain electrodes, the storage capacitor conductive patterns being connected to the second gate lines through the first contact holes;

a passivation layer covering the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern;

second contact holes formed at the passivation layer while exposing the drain electrodes; and

pixel electrodes formed at the passivation layer while being connected to the drain electrodes through the second contact holes, the pixel electrodes being overlapped with the storage capacitor conductive patterns to thereby form first storage capacitors while being partially overlapped with the second gate lines to thereby form second storage capacitors.

35. A liquid crystal display comprising:

the thin film transistor array panel of claim 34;

a counter substrate facing the thin film transistor array panel; and

a liquid crystal layer sandwiched between the thin film transistor array panel and the counter panel.

36. The liquid crystal display of claim 35 wherein the first and the second storage capacitors have an electrostatic capacitance greater than the electrostatic capacitance of the liquid crystal layer by 90% or more.

37. A method of fabricating a thin film transistor array panel, the method comprising the steps of:

forming a gate line assembly and a storage capacitor line assembly on an insulating substrate such that the gate line assembly has gate lines and gate electrodes;

forming a gate insulating layer such that the gate insulating layer covers the gate line assembly and the storage capacitor line assembly;

forming a semiconductor pattern on the gate insulating layer;

forming a data line assembly and storage capacitor conductive patterns on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has data lines, source electrodes and drain electrodes, and the storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors;

forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern;

forming first and second contact holes at the passivation layer such that the first and the second contact holes expose the drain electrodes and the storage capacitor conductive patterns, respectively; and

forming pixel electrodes on the passivation layer such that the pixel electrodes are connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes while forming second storage capacitors in association with parts of the storage capacitor lines assembly.

38. The method of claim 37 wherein the storage capacitor line assembly has storage capacitor electrode lines proceeding parallel to the gate lines, and storage capacitor electrode patterns connected to the storage capacitor electrode lines.

39. A method of fabricating a thin film transistor array panel, the method comprising the steps of:

forming a gate line assembly on an insulating substrate such that the gate line assembly has first gate lines, gate electrodes connected to the first gate lines, and second gate lines spaced apart from the first gate lines with a predetermined distance while proceeding parallel to the first gate lines;

forming a gate insulating layer such that the gate insulating layer covers the gate line assembly;

forming a semiconductor pattern on the gate insulating layer such that the semiconductor pattern is overlapped with the gate electrodes;

forming a data line assembly and storage capacitor conductive patterns on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has data lines crossing over the first and the second gate lines, source electrodes and drain electrodes, and the storage capacitor conductive patterns are partially overlapped with the second gate lines to thereby form first storage capacitors;

forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern;

forming first and second contact holes at the passivation layer such that the first and the second contact holes expose the drain electrodes and the storage capacitor conductive patterns, respectively; and

forming pixel electrodes on the passivation layer such that the pixel electrodes are connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes while forming second storage capacitors in association with parts of the second gate lines.

40. A method of fabricating a thin film transistor array panel, the method comprising the steps of:

forming a gate line assembly and storage capacitor electrode lines on an insulating substrate such that the gate line assembly has gate lines and gate electrodes;

forming a gate insulating layer such that the gate insulating layer covers the gate line assembly and the storage capacitor electrode lines;

forming first contact holes at the gate insulating layer such that the first contact holes expose the storage capacitor electrode lines;

forming a semiconductor pattern on the gate insulating layer such that the semiconductor pattern is overlapped with the gate electrodes;

forming a data line assembly and storage capacitor conductive patterns on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has data lines, source electrodes and drain electrodes, and the storage capacitor conductive patterns are connected to the storage capacitor electrode lines through the first contact holes;

forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern;

forming second contact holes at the passivation layer such that the second contact holes expose the drain electrodes; and

forming pixel electrodes on the passivation layer such that the pixel electrodes are connected to the drain electrodes through the second contact holes, the pixel electrodes being overlapped with the storage capacitor conductive patterns to thereby form first storage capacitors while being partially overlapped with the storage capacitor electrode lines to thereby form second storage capacitors.

41. A method of fabricating a thin film transistor array panel, the method comprising the steps of:

forming a gate line assembly on an insulating substrate such that the gate line assembly has first gate lines, gate electrodes connected to the first gate lines, and second gate lines spaced apart from the first gate lines with a predetermined distance while proceeding parallel to the first gate lines;

forming a gate insulating layer such that the gate insulating layer covers the gate line assembly;

forming first contact holes at the gate insulating layer such that the first contact holes partially expose the second gate lines;

forming a semiconductor pattern on the gate insulating layer such that the semiconductor pattern is overlapped with the gate electrodes;

forming a data line assembly and storage capacitor conductive patterns on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has data lines crossing over the first and the second gate lines, source electrodes and drain electrodes, and the storage capacitor conductive patterns are connected to the second gate lines through the first contact holes;

forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern;

forming second contact holes at the passivation layer such that the second contact holes expose the drain electrodes; and

forming pixel electrodes on the passivation layer such that the pixel electrodes are connected to the drain electrodes through the second contact holes, the pixel electrodes being overlapped with the storage capacitor conductive patterns to thereby form first storage capacitors while being partially overlapped with the second gate lines to thereby form second storage capacitors.