ESD protection with uniform substrate bias

• US 20040114287A1
• Filed: 12/11/2002
• Published: 06/17/2004
• Est. Priority Date: 12/11/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Salling, Craig T., Cline, Roger A.
• Granted Patent: US 6,900,969 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0277 involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor

Abstract

Protection circuitry (100) for protecting an integrated circuit against an ESD pulse is provided. The protection circuitry (100) includes a discharge circuitry (101) on a substrate (106) that discharges an ESD pulse to the integrated circuit to ground (104a). The protection circuitry (100) also includes a drive circuitry (102) that uses a portion of the ESD pulse voltage to bias the substrate (106) using a first guard ring (110) in the substrate (106), which surrounds the discharge circuitry (101) and drive circuitry (102). The protection circuitry (100) further includes a second guard ring (120) in substrate (106), which surrounds the first guard ring (110) and connects to Vss/ground potential (104c), thereby providing uniformity of the substrate bias.

Claims

1. Integrated circuit component on a substrate, said component requiring a uniformly distributed voltage bias in said substrate, comprising:

a sub-circuitry generating said voltage;

a distributor shaped as a ring surrounding said component, said distributor operable to spread said voltage to said substrate;

an equalizer surrounding said distributor, said equalizer enforcing said required uniform bias distribution throughout said substrate correlated with said component.

10. The integrated circuit component according to claim 1 wherein said substrate is selected from a group consisting of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, and any other semiconductor material commonly used in manufacturing.

2. Protection circuitry for protecting an integrated circuit against an ESD pulse, comprising:

a discharge circuitry on a substrate operable to discharge said ESD pulse to ground;

a drive circuitry operable to use a portion of said ESD pulse voltage to provide current, and consequently voltage drop, for said substrate of said discharge circuitry;

said drive circuitry having a first guard ring surrounding said drive circuitry, said first guard ring operable to supply bias to said substrate; and

a second guard ring on said substrate, surrounding said first guard ring and connected to Vss/ground potential, said second guard ring providing uniformity of said substrate bias and isotropic current flow, thereby allowing said discharge circuitry to turn on uniformly and discharge said ESD pulse effectively.

3. The protection circuitry according to claim 2 wherein said second guard ring surrounds said first guard ring at equal distance along all sections.

4. The protection circuitry according to claim 3 wherein said equal distance is between 5 and 10 μ

m.

5. The protection circuitry according to claim 2 wherein said second guard ring surrounds the discharge circuitry as well as the drive circuitry.

6. The protection circuitry according to claim 2 wherein the effectiveness of said discharge circuitry is based primarily on the uniformity of the voltage drop and only secondarily on the size of voltage drop.

7. The protection circuitry according to claim 2 wherein said discharge circuitry may be an nMOS circuit, a pMOS circuit;

an SCR, or any other device based on substrate bias.

8. The protection circuitry according to claim 2 wherein said first guard ring and said second guard ring are made of heavily doped semiconductor material contacted by metal.

9. The protection circuitry according to claim 2 wherein said first guard ring and said second guard ring are configured as closed rings to insure simultaneous timing as well as uniformity of said voltage drop.

11. The protection circuitry according to claim 2 wherein said drive circuitry comprises:

an input for receiving a portion of an ESD pulse energy;

a transistor having an input, gate, and an output, said transistor being a single transistor or a cascoded transistor, said transistor operable to provide a portion of an ESD pulse to a substrate bias generator;

said substrate bias generator comprising;

a resistor connected between said input and said substrate; and

said first guard ring coupled to said resistor such that a voltage drop across said resistor is impressed on said first guard ring, thereby biasing said discharge circuit substrate.

12. The protection circuitry according to claim 2 further comprising said second grounded guard ring operable to act as a collector of injected carriers for prevention of latch-up.

13. The protection circuitry according to claim 2 further comprising a third guard ring surrounding said second grounded guard ring, said third guard ring made of material of opposite conductivity to said second guard ring and tied to power, whereby minority carriers in said substrate can be collected for providing latch-up robustness.

14. The protection circuitry according to claim 13 wherein said third guard ring, in combination with said second guard ring, reduces switching noise in said substrate of said protection circuitry.