Compaction scheme in NVM

• US 20040114437A1
• Filed: 12/13/2002
• Published: 06/17/2004
• Est. Priority Date: 12/13/2002
• Status: Active Grant

• Current Assignee: Progressive Semiconductor Solutions LLC (Acacia Research Corporation)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Li, Chi Nan Brian
• Granted Patent: US 6,836,435 B2
• Time in Patent Office: Days
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

A method of erasing a semiconductor nonvolatile memory (NVM) so as to compact the distribution of cell erased threshold voltages within a restricted range around a target erased threshold voltage. Erase pulses are applied to NVM cells until a determination is made by, for example, sensing total column source current that adequate erasure has been realized. An optional soft program signal may be applied subsequent to each erase pulse in order to impede over-erasure. Once erasure has been verified, the distribution of erased threshold voltages is compacted by sustaining, for a predetermined length of time, the simultaneous application of a gate voltage that is equal to the target erased threshold voltage and a highly positive drain voltage.

Claims

1. A method of erasing a nonvolatile memory (NVM) that includes a plurality of NVM cells, each cell having a gate, a source, a drain, and a channel between the source and the drain, the method comprising:

(a) applying an erase pulse to the NVM cell;

(b) determining whether erasure was effective; and

(c) if erasure is determined to be effective, compacting threshold voltages of NVM cells.

2. A method of erasing an NVM as defined in claim 1, wherein compacting the threshold voltages of erased NVM cell is effected by applying to NVM cells a gate voltage that is approximately equal to a target erased threshold voltage and sustaining the application of the gate voltage for a predetermined time.

3. A method of erasing an NVM as defined in claim 2, wherein the predetermined time is a length of time sufficient to cause the distribution of erased threshold voltages NVM cells to be confined to a specified range.

4. A method of erasing an NVM as defined in claim 3, wherein the predetermined length of time is sufficient to balance channel electrons and holes in charge-storage layer of the NVM cells.

5. A method of erasing an NVM as defined in claim 1, wherein a soft program step is performed on the NVM after step (a) and prior to step (c).

6. A method of erasing an NVM as defined in claim 5, wherein compacting the threshold voltages of erased NVM cell is effected by applying to NVM cells a gate voltage that is approximately equal to a target erased threshold voltage and sustaining the application of the gate voltage for a predetermined time.

7. A method of erasing an NVM as defined in claim 5, wherein a soft program step is performed on the NVM after step (a) and prior to step (b).

8. A method of erasing an NVM as defined in claim 7, wherein compacting the threshold voltages of erased NVM cell is effected by applying to NVM cells a gate voltage that is approximately equal to a target erased threshold voltage and sustaining the application of the gate voltage for a predetermined time.

9. A method of erasing an NVM as defined in claim 8, wherein the predetermined time is a length of time sufficient to cause the distribution of erased threshold voltages NVM cells to be confined to a specified range.

10. A method of erasing an NVM as defined in claim 9, wherein the predetermined length of time is sufficient to balance channel electrons and holes in charge-storage layer of the NVM cells.

11. An array of nonvolatile memory (NVM) cells arranged in a plurality of columns and plurality of rows, each memory cell comprising:

body of semiconductor material having a surface;

a drain formed in the body beneath the surface;

a source formed in the body beneath the surface, the drain and the source defining a channel therebetween;

a gate dielectric disposed on the surface over at least a portion of the channel, the gate dielectric comprising an ONO stack;

a gate conductor overlying the gate dielectric;

a first bit line coupled to the drain of each NVM cell in a first column of the plurality of columns;

a second bit line coupled to the drain of each NVM cell in a second column of the plurality of columns;

a first word line coupled to the gate conductor of each memory cell in a first row of the plurality of rows;

a second word line coupled to the gate conductor of each memory cell in a second row of the plurality of rows;

a source line coupled to the source of each NVM cell in the first row and to the source of each NVM cell in the second row;

a first voltage source coupled to both the first word line and to the second word line, the first voltage source providing first voltage approximately equal to a target erased threshold voltage; and

a second voltage source coupled to the first bit line, the second voltage source providing a second voltage that is greater than the first voltage

13. A method of erasing a nonvolatile memory (NVM) cell having a gate, a source, and a drain, the method comprising:

applying an erase signal to the NVM cell;

applying a signal to the NVM cell so as to impede over-erasure of the cell;

determining whether the NVM cell is effectively erased; and

applying a compaction signal to the NVM cell.

12. An array of NVM cells as defined in claim 13, wherein each of the NVM cells has been subjected to an erase operation that has not been succeeded by a program operation and the NVM cells exhibit a distribution of erased threshold voltages that is compacted about the target erased threshold voltage.

14. A method of erasing an NVM cell as defined in claim 13, wherein over-erasure of the NVM cell is impeded by applying a soft program signal to the NVM cell.

15. A method of erasing an NVM cell as defined in claim 14, wherein the soft program signal comprises a voltage approximately equal to a target most-erased threshold voltage coupled to the gate and a positive voltage coupled to the drain.

16. A method of erasing an NVM cell as defined in claim 13, wherein the compaction signal comprises a voltage approximately equal to a target erased threshold voltage coupled to the gate and a positive voltage coupled to the drain.

17. A method of erasing an NVM cell as defined in claim 16, wherein the compaction signal is applied to the NVM cell for a time adequate to cause the erased threshold voltage of the cell to have a value within a predetermined range around the erased target voltage.

18. A method of erasing an NVM cell as defined in claim 16, wherein current flowing between the drain and the source is sensed in order to determine whether the NVM cell is effectively erased.

19. A method of erasing an NVM cell as defined in claim 16, wherein over-erasure of the NVM cell is impeded by applying a soft program signal to the NVM cell.

20. A method of erasing an NVM cell as defined in claim 19, wherein the soft program signal comprises a voltage approximately equal to a target most-erased threshold voltage coupled to the gate and a positive voltage coupled to the drain.

21. In a semiconductor nonvolatile memory (NVM) that comprises a plurality of NVM cells, each all having a drain, a source, a channel between the gate and the source, a gate dielectric in the form of an ONO stack disposed over at least a portion of the channel, and a gate conductor overlying the gate dielectric, a method of erasing the NVM by successively performing the steps:

(a) applying an erase pulse to an NVM cell;

(b) soft programming the NVM cell;

(c) determining whether the NVM cell is erased;

(d) repeating steps (a), (b) and (c); and

(e) applying to the gate conductor, for a predetermined length of time, a target erased threshold voltage.

22. A method as defined in claim 21, wherein the target erased threshold voltage is applied to the gate conductor for a length of time that causes a distribution of erased threshold voltages of NVM cells to be substantially confined to a predetermined range around the target erased threshold voltage.

23. A method as defined in claim 22, wherein the target erased threshold voltage is applied to the gate conductor for a length of time that causes holes and electrons in a charge-storage layer of the ONO stack to become substantially balanced.

24. A method as defined in claim 21, wherein soft programming the NVM cell causes the NVM cell threshold voltage to be moved toward a target programmed threshold voltage.

25. A method as defined in claim 24, wherein the target erased threshold voltage is applied to the gate conductor for a length of time that causes a distribution of erased threshold voltages of NVM cells to be substantially confined to a predetermined range around the target erased threshold voltage.

26. A method as defined in claim 25, wherein the target erased threshold voltage is applied to the gate conductor for a length of time that causes holes and electrons in a charge-storage layer of the ONO stack to become substantially balanced.

27. A method as defined in claim 26, wherein step (c) comprises reading the NVM cell and determining a current conducted by the NVM cell.