Reconfigurable memory controller

• US 20040117566A1
• Filed: 12/11/2002
• Published: 06/17/2004
• Est. Priority Date: 12/11/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Delp, Gary, Nation, George, McClannahan, Gary
• Granted Patent: US 7,043,611 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

The present invention is directed to a reconfigurable memory controller. A reconfigurable memory controller may include a plurality of communicatively coupled memory controllers. The plurality of communicatively coupled memory controllers is reconfigurable so that the controllers are groupable into a first memory configuration and a second memory configuration. The first memory configuration has a different bandwidth grouping than the second memory configuration.

Claims

1. A reconfigurable memory controller, comprising:

a plurality of communicatively coupled memory controllers implemented as configurable logic, wherein the plurality of communicatively coupled memory controllers are reconfigurable so that the controllers are groupable into a first memory configuration and a second memory configuration, the first memory configuration having a different bandwidth grouping than the second memory configuration.

2. The memory controller as described in claim 1, wherein the reconfigurable memory controller is included in a programmable chip platform.

3. The memory controller as described in claim 1, wherein the reconfigurable memory controller is communicatively coupled to an external DRAM.

4. The memory controller as described in claim 1, wherein the plurality of memory controllers includes a first memory controller and a second memory controller.

5. The memory controller as described in claim 4, wherein at least one of the technology type and speed of the first memory controller is different from the second memory controller.

6. The memory controller as described in claim 4, wherein at least one of the width and depth of a memory array for the first memory controller is different from the second memory controller.

7. The memory controller as described in claim 4, wherein memory operations supported by the first memory controller are different than the second memory controller.

8. The memory controller as described in claim 4, wherein at least one of the type, speed and width of interface to other logic included on a programmable chip platform including the flexible memory controller connected to the first memory controller is different than the second memory controller.

9. The memory controller as described in claim 4, wherein the bandwidth of the first configuration is different than the second configuration.

10. A reconfigurable memory controller, comprising:

a plurality of communicatively coupled memory controllers including a first memory controller, a second memory controller, and a third memory controller, wherein the plurality of communicatively coupled memory controllers are reconfigurable so that the first memory controller and the second memory controller are groupable into a first memory configuration, and the first memory controller and the third memory controller are groupable into a second memory configuration, the first memory configuration being distinct from the second memory configuration.

11. The memory controller as described in claim 10, wherein the reconfigurable memory controller is included in a programmable chip platform.

12. The memory controller as described in claim 10, wherein the reconfigurable memory controller is communicatively coupled to an external DRAM.

13. The memory controller as described in claim 10, wherein distinct includes at least one of the width and depth of a memory array for the first memory controller is different from the second memory controller.

14. The memory controller as described in claim 10, wherein distinct includes memory operations supported by the first memory controller are different than the second memory controller.

15. The memory controller as described in claim 10, wherein distinct includes at least one of the type, speed and width of interface to other logic included on a programmable chip platform including the flexible memory controller connected to the first memory controller is different than the second memory controller.

16. The memory controller as described in claim 10, wherein distinct includes the bandwidth of the first configuration is different than the second configuration.

17. A system, comprising:

a programmable chip platform having a reconfigurable memory controller including a plurality of communicatively coupled memory controllers, wherein the plurality of communicatively coupled memory controllers are flexibly configurable so that the controllers are groupable into a first memory configuration and a second memory configuration, the first memory configuration having a different bandwidth grouping than the second memory configuration; and

an external memory communicatively coupled to the programmable chip platform, wherein the flexible memory controller is suitable for controlling operations of the external memory.

18. The system as described in claim 17, wherein the reconfigurable memory controller is included in a programmable chip platform.

19. The system as described in claim 17, wherein the reconfigurable memory controller is communicatively coupled to an external DRAM.

20. The system as described in claim 17, wherein the plurality of memory controllers includes a first memory controller and a second memory controller.

21. The system as described in claim 20, wherein at least one of the technology type and speed of the first memory controller is different from the second memory controller.

22. The system as described in claim 20, wherein at least one of the width and depth of a memory array for the first memory controller is different from the second memory controller.

23. The system as described in claim 20, wherein memory operations supported by the first memory controller are different than the second memory controller.

24. The system as described in claim 20, wherein at least one of the type, speed and width of interface to other logic included on a programmable chip platform including the flexible memory controller connected to the first memory controller is different than the second memory controller.

25. The system as described in claim 20, wherein the bandwidth of the first configuration is different than the second configuration.

26. A method for reconfiguring a memory controller to support different configurations, comprising:

providing a reconfigurable memory controller having a plurality of communicatively coupled memory controllers, the plurality of memory controllers being groupable;

configuring the plurality of communicatively coupled memory controllers into a first memory configuration, the first memory configuration having a first grouping of memory controllers and a second grouping of memory controllers, the first grouping of memory controllers having a first bandwidth and the second grouping of memory controllers having a second bandwidth; and

reconfiguring the plurality of communicatively coupled memory controllers into a second memory configuration, the second memory configuration having a third grouping of memory controllers and a fourth grouping of memory controllers, the third grouping of memory controllers having a third bandwidth and the fourth grouping of memory controllers having a fourth bandwidth,

wherein the bandwidths as grouped by the first grouping and the second grouping of the first memory configuration are different from the bandwidths of the third grouping and the fourth grouping of the second memory configuration.

27. The method as described in claim 26, wherein the reconfigurable memory controller is included in a programmable chip platform.

28. The method as described in claim 26, wherein the reconfigurable memory controller is communicatively coupled to an external DRAM.