Reclaiming existing fields in address translation data structures to extend control over memory acceses

• US 20040117593A1
• Filed: 12/12/2002
• Published: 06/17/2004
• Est. Priority Date: 12/12/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Neiger, Gilbert, Bennett, Steven M., Uhlig, Richard, Jeyasingh, Stalinselvaraj, Kagi, Alain, Cota-Robles, Erik, Kozuch, Michael
• Granted Patent: US 7,073,042 B2
• Time in Patent Office: Days
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism

Abstract

In one embodiment, when it is determined that a modification of content of an active address translation data structure is required, an entry in the active address translation data structure is modified to conform to a corresponding entry in a guest address translation data structure. During the modification, a bit field including one or more access control indicators in the entry of the active address translation data structure is not overwritten with corresponding data from the guest address translation data structure.

Claims

1. A method comprising:

determining that a modification of content of an active address translation data structure is required; and

refraining from overwriting a portion of an entry in the active address translation data structure while modifying the entry in the active address translation data structure to conform to a corresponding entry in a guest address translation data structure, the portion of the entry in the active address translation data structure including at least one access control indicator.

2. The method of claim 1 wherein the content of the active address translation data structure is used by a processor to cache address translations in a translation-lookaside buffer (TLB).

3. The method of claim 1 wherein the guest address translation data structure is used by guest software for address translation operations.

4. The method of claim 1 wherein the active address translation data structure is managed by a virtual machine monitor (VMM).

5. The method of claim 1 further comprising:

setting the at least one access control indicator to a specific value.

6. The method of claim 1 wherein the active address translation data structure is an active page-table hierarchy.

7. The method of claim 6 wherein:

the entry in the active address translation data structure is any one of a page-table entry and a page-directory entry; and

the at least one access control indicator is at least one software-available bit within the entry.

8. The method of claim 6 wherein the at least one access control indicator includes a guest-host indicator controlling access to a corresponding page in the page-table hierarchy by guest software.

9. The method of claim 6 wherein the at least one access control indicator includes an execute-privilege indicator controlling execution of instructions from a corresponding page in the page-table hierarchy and a read-privilege indicator controlling read accesses to the corresponding page in the page-table hierarchy.

10. The method of claim 9 wherein a read/write bit is re-interpreted as a write privilege indicator controlling write accesses to the corresponding page in the page-table hierarchy.

11. The method of claim 6 wherein the at least one access control indicator includes a privilege-level access indicator controlling accesses to a corresponding page in the page-table hierarchy by code running at a specific privilege level.

12. An apparatus comprising:

a guest address translation data structure to translate virtual memory addresses into physical memory addresses by guest software;

an active address translation data structure to derive partial content from the guest address translation data structure, the partial content excluding at least one access control indicator within each of a plurality of entries in the guest address translation data structure; and

a translation-look aside buffer (TLB) to store address translations obtained from the active address translation data structure by a processor.

13. The apparatus of claim 12 wherein the active address translation data structure is managed by a virtual machine monitor (VMM).

14. The apparatus of claim 13 wherein the VMM is to set at least one access control indicator in an entry of the active address translation data structure to a specific value.

15. The apparatus of claim 12 wherein the active address translation data structure is an active page-table hierarchy.

16. The apparatus of claim 15 wherein:

the entry in the active address translation data structure is any one of a page-table entry and a page-directory entry; and

the at least one access control indicator is at least one software-available bit within the entry.

17. The apparatus of claim 15 wherein the at least one access control indicator in the entry of the active address translation data structure includes a guest-host indicator controlling access to a corresponding page in the page-table hierarchy by guest software.

18. The apparatus of claim 15 wherein the at least one access control indicator in the entry of the active address translation data structure includes an execute-privilege indicator controlling execution of instructions from a corresponding page in the page-table hierarchy and a read-privilege indicator controlling read accesses to the corresponding page in the page-table hierarchy.

19. The apparatus of claim 18 wherein a read/write bit is re-interpreted as a write privilege indicator controlling write accesses to the corresponding page in the page-table hierarchy.

20. The apparatus of claim 15 wherein the at least one access control indicator in the entry of the active address translation data structure includes a privilege-level access indicator controlling accesses to a corresponding page in the page-table hierarchy by code running at a specific privilege level.

22. The machine-readable medium of claim 20 wherein the content of the active address translation data structure is used by a processor to cache address translations in a translation-lookaside buffer (TLB).

23. The machine-readable medium of claim 20 wherein the guest address translation data structure is used by guest software for address translation operations.

24. The machine-readable medium of claim 20 wherein the active address translation data structure is managed by a virtual machine monitor (VMM).

25. The machine-readable medium of claim 20 wherein the active address translation data structure is an active page-table hierarchy.

26. The machine-readable medium of claim 25 wherein:

the entry in the active address translation data structure is any one of a page-table entry and a page-directory entry; and

the at least one access control indicator is at least one software-available bit within the entry.

21. A machine-readable medium containing instructions which, when executed by a processing system, cause the processing system to perform a method, the method comprising:

determining that a modification of content of an active address translation data structure is required; and

refraining from overwriting a portion of an entry in the active address translation data structure while modifying the entry in the active address translation data structure to conform to a corresponding entry in a guest address translation data structure, the portion of the entry in the active address translation data structure including at least one access control indicator.

27. A system comprising:

a processing system; and

a memory, coupled to the processing system, to store instructions, which when executed by the processing system, cause the processing system to determine that a modification of content of an active address translation data structure is required, and to refrain from overwriting a portion of an entry in the active address translation data structure while modifying the entry in the active address translation data structure to conform to a corresponding entry in a guest address translation data structure, the portion of the entry in the active address translation data structure including at least one access control indicator.

28. The system of claim 27 wherein the content of the active address translation data structure is used by a processor to cache address translations in a translation-lookaside buffer (TLB).

29. The system of claim 27 wherein the guest address translation data structure is used by guest software for address translation operations.

30. The system of claim 29 wherein the active address translation data structure is managed by a virtual machine monitor (VMM).