Method and apparatus for pausing execution in a processor or the like
First Claim
1. A method of pausing execution of instructions in a thread, comprising:
- determining if a next instruction for a first thread is an instruction of a first type; and
preventing instructions of said first thread from being processed for execution for a period of time while instructions from a second thread can be processed for execution.
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Abstract
A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET instruction and a READ instruction. When a SET flag is retrieved for a given thread, the SET instruction sets a Bit flag in memory indicating that execution for the thread has been paused. The SET instruction is placed in the pipeline for execution. The following READ instruction for that thread, however, is prevented from entering the pipeline until, the SET instruction is executed and retired (resulting in a clearing of the Bit flag). Once the Bit flag has been cleared, the READ instruction is placed in the pipeline for execution. During the time that processing of one thread is paused, the execution of other threads may continue.
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Citations
20 Claims
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1. A method of pausing execution of instructions in a thread, comprising:
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determining if a next instruction for a first thread is an instruction of a first type; and
preventing instructions of said first thread from being processed for execution for a period of time while instructions from a second thread can be processed for execution. - View Dependent Claims (2, 3, 4, 5)
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6. A method of pausing execution of instructions in a thread, comprising:
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determining if a next instruction for a first thread is an instruction of a first type;
initiating a counter; and
preventing instructions of said first thread from being processed for execution until said counter reaches a predetermined value. - View Dependent Claims (7, 8)
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9. A method of reducing power consumption in a processor system comprising:
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receiving a pause instruction from a first thread at a decode unit in said processor system;
preventing instructions of said first thread from being processed for execution for a period of time while instructions from a second thread can be processed for execution. - View Dependent Claims (10)
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11. An apparatus pausing execution of instructions in a thread, comprising:
a decode unit to determine if a next instruction for a first thread is an instruction of a first type, said decode unit to prevent instructions of said first thread from being processed for execution for a period of time while instructions from a second thread can be processed for execution. - View Dependent Claims (12, 13, 14, 15)
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16. An apparatus for pausing execution of instructions in a thread, comprising:
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a decode unit to determine if a next instruction for a first thread is an instruction of a first type;
a counter that is initiated when said next instruction for a first thread is an instruction of a first type, said decode unit to prevent instructions of said first thread from being processed for execution until said counter reaches a predetermined value. - View Dependent Claims (17, 18)
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19. An apparatus for reducing power consumption in a processor system comprising:
a processor system including a decode unit to receive a pause instruction from a first thread in said processor system, said decode unit to prevent instructions of said first thread from being processed for execution for a period of time while instructions from a second thread can be processed for execution. - View Dependent Claims (20)
Specification