System and method for implementing an integrated circuit having dynamically variable power limit

• US 20040117680A1
• Filed: 12/16/2002
• Published: 06/17/2004
• Est. Priority Date: 12/16/2002
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Naffziger, Samuel
• Granted Patent: US 8,086,884 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit having a dynamically variable power limit is provided. The integrated circuit comprises power management logic operable to receive notification of a dynamically set power limit value and operable to dynamically regulate the integrated circuit'"'"'s power consumption to comply with the dynamically set power limit value.

Claims

1. An integrated circuit having a dynamically variable power limit comprising:

power management logic operable to receive notification of a dynamically set power limit value and operable to dynamically regulate the integrated circuit'"'"'s power consumption to comply with the dynamically set power limit value.

2. The integrated circuit of claim 1 wherein said power management logic is at least temporarily communicatively coupled to a power limit controller from which said power management logic receives said notification of said dynamically set power limit value.

3. The integrated circuit of claim 1 wherein said dynamically set power limit value comprises a value less than said integrated circuit'"'"'s maximum power limit value.

4. The integrated circuit of claim 1 wherein said integrated circuit comprises core circuitry for performing processing synchronous with a clock signal, and wherein said power management logic is operable to dynamically vary said clock signal'"'"'s frequency to regulate the integrated circuit'"'"'s power consumption.

5. The integrated circuit of claim 4 wherein said power management logic is operable to dynamically vary said clock signal'"'"'s frequency based at least in part on voltage being consumed by said integrated circuit.

6. The integrated circuit of claim 5 wherein said power management logic comprises a voltage controlled oscillator for generating said clock signal.

7. The integrated circuit of claim 4 wherein said power management logic is operable to dynamically vary said clock signal'"'"'s frequency to provide optimum frequency without said integrated circuit'"'"'s power consumption exceeding said dynamically set power limit value.

8. The integrated circuit of claim 4 further comprising:

a mapping structure that maps different power limit values to corresponding clock signal frequency values that are predictably achievable by the integrated circuit without the integrated circuit'"'"'s power consumption exceeding the corresponding power limit value.

9. The integrated circuit of claim 8 wherein said mapping structure comprises said clock signal frequency values that are each a maximum frequency value that is consistently achievable by said integrated circuit without exceeding a corresponding power limit value.

10. The integrated circuit of claim 8 wherein said power management logic is communicatively coupled to said mapping structure, and wherein said power management logic is operable to, responsive to receiving notification of said dynamically set power limit value, access said mapping structure and determine a maximum clock signal frequency to be used under the dynamically set power limit value.

11. The integrated circuit of claim 1 wherein said integrated circuit is selected from the group consisting of:

microprocessor, embedded controller, network router, graphics processor, and any application specific integrated circuit (ASIC).

12. The integrated circuit of claim 1 wherein said power management logic is communicatively coupled to a power supply that provides a supply voltage to the integrated circuit, and wherein said power management logic is operable to dynamically vary the supply voltage supplied by said power supply to the integrated circuit to dynamically regulate the integrated circuit'"'"'s power consumption.

13. A system comprising:

means for processing a signal synchronous with a clock signal; and

means for dynamically setting the power limit of the processing means to a desired value, wherein the processing means comprises means for self-regulating its power consumption to comply with a dynamically set power limit.

14. The system of claim 13 wherein said desired value comprises a value less than said processing means'"'"' maximum power limit value.

15. The system of claim 13 wherein said processing means comprises an integrated circuit that includes core circuitry for performing said processing synchronous with said clock signal, and wherein said means for self-regulating its power consumption comprises a means for dynamically varying said clock signal'"'"'s frequency to regulate the integrated circuit'"'"'s power consumption.

16. The system of claim 15 wherein said means for dynamically varying said clock signal'"'"'s frequency comprises a means for varying said clock signal'"'"'s frequency based at least in part on voltage being consumed by said integrated circuit.

17. The system of claim 15 wherein said means for dynamically varying said clock signal'"'"'s frequency is operable to vary said clock signal'"'"'s frequency to provide optimum frequency without said integrated circuit'"'"'s power consumption exceeding said dynamically set power limit value.

18. The system of claim 15 further comprising:

means for mapping different power limit values to corresponding clock signal frequency values that are predictably achievable by the integrated circuit without the integrated circuit'"'"'s power consumption exceeding the corresponding power limit value.

19. The system of claim 18 wherein the mapping means comprises said clock signal frequency values that are each a maximum frequency value that is consistently achievable by said integrated circuit without exceeding a corresponding power limit value.

20. The system of claim 18 wherein said means for self-regulating its power consumption is communicatively coupled to the mapping means, and wherein said means for self-regulating its power consumption is operable to, responsive to receiving notification of said desired power limit value, access the mapping means and determine a maximum clock signal frequency to be used under the desired power limit value.

21. The system of claim 13 further comprising:

means for supplying a supply voltage to the processing means, wherein the self-regulating means is operable to dynamically control the supplying means to dynamically vary said supply voltage.

22. An integrated circuit having a dynamically variable power limit comprising:

core circuitry for processing, wherein said processing is synchronous with a clock signal;

mapping structure that maps different power limit values to corresponding frequency values of said clock signal; and

power management logic operable to

receive notification of a dynamically set power limit value for said integrated circuit,

determine based at least in part on said mapping structure a frequency value of said clock signal for complying with said dynamically set power limit value, and

dynamically set said clock signal to a determined frequency value for managing power consumption of said integrated circuit to comply with said dynamically set power limit value.

23. The integrated circuit of claim 22 wherein said power management logic is operable to dynamically vary said clock signal'"'"'s frequency based at least in part on the amount of voltage supplied to said core circuitry.

24. The integrated circuit of claim 23 wherein said power management logic comprises a voltage controlled oscillator for generating said clock signal.

25. The integrated circuit of claim 24 wherein a common voltage is supplied to said voltage controlled oscillator and said core circuitry.

26. The integrated circuit of claim 22 wherein said mapping structure comprises said clock signal frequency values that are each a maximum frequency value that is consistently achievable by said integrated circuit without exceeding a corresponding power limit value.

27. The integrated circuit of claim 22 wherein said power management logic is operable to determine, based at least in part on said mapping structure, a maximum frequency of said clock signal that is predictably achievable by said integrated circuit without exceeding a dynamically set power limit value.

28. The integrated circuit of claim 22 wherein said power management logic is communicatively coupled to a power supply that provides a supply voltage to the integrated circuit, and wherein said power management logic is operable to dynamically vary the supply voltage supplied by said power supply to the integrated circuit to dynamically regulate the integrated circuit'"'"'s power consumption.

29. A method for providing an integrated circuit having a dynamically variable power limit and predictable performance, said method comprising:

characterizing a plurality of integrated circuit units of a particular design that comprise core circuitry for processing, wherein said processing is synchronous with a clock signal and wherein said characterizing determines, for each of a plurality of different power limit values of said integrated circuit units, a predictable clock signal frequency that is achievable within a tolerance by all of said plurality of integrated circuit units of said particular design without their power consumption exceeding the corresponding power limit value;

constructing a mapping structure that maps the determined predictable clock signal frequencies to corresponding power limit values; and

implementing the mapping structure in a system that includes an integrated circuit of the particular design for use in dynamically varying the integrated circuit'"'"'s power limit.

30. The method of claim 29 wherein said particular design of said integrated circuit comprises a particular design of an integrated circuit selected from the group consisting of:

microprocessor, embedded controller, network router, graphics processor, and any application specific integrated circuit (ASIC).

31. The method of claim 29 wherein said plurality of different power limit values comprises a range of power limit values.

32. The method of claim 29 wherein said characterizing said plurality of integrated circuits comprises:

for a first of said plurality of different power limit values, determining for each of the plurality of integrated circuit units a maximum clock signal frequency that the integrated circuit unit can utilize without its power limit exceeding said first of said plurality of different power limit values;

analyzing the determined maximum clock signal frequencies that the plurality of integrated circuit units can utilize to identify a maximum clock signal frequency that can be utilized within said tolerance by all of the plurality of integrated circuit units without any of their power limits exceeding said first of said plurality of different power limit values; and

using the identified maximum clock signal frequency that can be utilized within said tolerance by all of the plurality of integrated circuit units as the predictable clock signal frequency for said first of said plurality of different power limit values.

33. The method of claim 29 wherein said implementing the mapping structure in a system that includes an integrated circuit of the particular design comprises:

implementing said mapping structure as part of said integrated circuit.

34. A method for dynamically varying an integrated circuit'"'"'s power limit, the method comprising:

receiving, at an integrated circuit, notification that its power limit setting is changed to a different value; and

said integrated circuit self-regulating its power consumption to comply with said different value of its power limit setting.

35. The method of claim 34 wherein said integrated circuit comprises core circuitry for processing synchronous with a clock signal, and wherein said integrated circuit self-regulating its power consumption comprises:

determining whether the different value is the integrated circuit'"'"'s maximum power limit setting; and

if the different value is not the integrated circuit'"'"'s maximum power limit setting, then determining a suitable clock signal frequency that is achievable by said integrated circuit to comply with the different value of the integrated circuit'"'"'s power limit.

36. The method of claim 34 wherein said integrated circuit comprises core circuitry for processing synchronous with a clock signal, and wherein said self-regulating its power consumption comprises changing said clock signal frequency.

37. The method of claim 36 wherein said self-regulating its power consumption comprises:

changing the maximum clock signal frequency of said integrated circuit to a value.

38. The method of claim 37 wherein said self-regulating its power consumption further comprises:

accessing a mapping structure that maps different power limit values to corresponding clock signal frequency values that are predictably achievable by the integrated circuit without the integrated circuit'"'"'s power consumption exceeding the corresponding power limit value.

39. The method of claim 38 wherein said self-regulating its power consumption further comprises:

determining from said mapping structure said maximum clock signal frequency.

40. The method of claim 37 wherein said self-regulating its power consumption further comprises:

dynamically varying said clock signal'"'"'s frequency from said value to provide optimum frequency without said integrated circuit'"'"'s power consumption exceeding said different value of the integrated circuit'"'"'s power limit.

41. The method of claim 40 wherein said self-regulating its power consumption further comprises:

dynamically varying said clock signal'"'"'s frequency from said value based at least in part on voltage being consumed by said integrated circuit.

42. The method of claim 34 wherein said integrated circuit self-regulating its power consumption comprises:

controlling a power supply that provides a supply voltage to the integrated circuit to dynamically change the supply voltage supplied by said power supply to the integrated circuit.